JTAG (IEEE 1149.1/1149.6) Assertion IP provides an efficient and smart way to verify the JTAG designs quickly without a testbench. The SmartDV's JTAG Assertion IP is fully compliant with standard JTAG Specification and provides the following features.
JTAG (IEEE 1149.1/1149.6) Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
JTAG (IEEE 1149.1/1149.6) Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Specification Compliance
- Supports Jtag protocol standard IEEE 1149.1 and IEEE 1149.6.
- Supports all the JTAG tap instructions.
- Supports programmable clock frequency of operation.
- Checks for following
- State based rules
- Active Command rules
- Read/Write to Instruction and data register Rules.
- Supports Instruction register and data register of size up to 64 bits.
- Proficiency to extend with user defined instructions and registers.
- Support all types of timing and protocol violation detection.
- Assertion IP features
- Assertion IP includes:
- System Verilog assertions
- System Verilog assumptions
- System Verilog cover properties
- Synthesizable Verilog Auxiliary code
- Support Master mode, Slave mode, Monitor mode and Constraint mode.
- Supports Simulation mode (stimulus from SmartDV JTAG VIP) and Formal mode (stimulus from Formal tool).
- Rich set of parameters to configure JTAG Assertion IP functionality.
- Benefits
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- Runs in every major formal and simulation environment.
- JTAG Assertion Env
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SmartDV's JTAG Assertion env contains following.
- Detailed documentation of Assertion IP usage.
- Documentation also contains User's Guide and Release notes.
