MIPI RFFE Verification IP provides an smart way to verify the MIPI RFFE bi-directional two-wire bus. The SmartDV's MIPI RFFE Verification IP is fully compliant with version 1.0,2.0,2.1 and 3.0 MIPI Alliance specification for RF Front-End Control Interface and provides the following features.
MIPI RFFE Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
MIPI RFFE Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Supports 1.0,2.0,2.1 and 3.0 MIPI RFFE Specification.
- Full MIPI RFFE Master and Slave functionality.
- Operates as a Master, Slave, or both.
- Monitor, Detects and notifies the testbench of all protocol and timing errors.
- Supports all topologies as per the MIPI RFFE specification.
- Supports multiple slaves.
- Compares read data with expected results.
- Supports following frames.
- Command Frame
- Data/Address Frame
- No Response Frame
- Bus ownership transfer
- Interrupt polling
- Master write and read
- Master context write and context read
- Various kind of Master and Slave errors generation.
- Undefined command frame
- Command frame with parity error
- Command frame length error
- Address frame with parity error
- Data frame with parity error
- Read of unused register
- Write of an unused register
- Read using the broadcast ID or a GSID
- Various errors in Bus ownership transfer
- Glitch monitor and injection.
- Support injection of glitch at all positions of SDATA
- Support injection of glitch at all positions of SCLK
- Supports detection of glitches
- Supports extended register read/writes.
- Supports interrupt summary and identification command sequence.
- Supports Master ownership handover.
- Support Master write and read sequence.
- Support Trigger and Extended trigger modes.
- Support Masked write command sequence.
- Support Silent Master initiated bus park.
- Support Interrupt capable slave.
- Support Synchronous read.
- Support Normal and Secondary operation mode.
- Support USID Programming Procedure 1,2 and 3.
- Support Group slave ID.
- Support Timed Trigger and Mappable Trigger.
- Support Bus Clocked Condition.
- Supports device enumeration.
- Supports Low power testing.
- Bus-accurate timing.
- Supports half speed.
- Callbacks in master, slave and monitor for various events.
- Status counters for various events in bus.
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
- Functional coverage of complete MIPI RFFE specs.
- MIPI RFFE Verification IP comes with complete testsuite to test every feature of MIPI RFFE specification.
- Benefits
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- Faster testbench development and more complete verification of MIPI RFFE designs.
- Easy to use command interface simplifies testbench control and configuration of master, slave and monitor
- Simplifies results analysis.
- Runs in every major simulation environment.
- MIPI RFFE Verification Env
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SmartDV's MIPI RFFE Verification env contains following.
- Complete regression suite containing all the MIPI RFFE testcases.
- Examples showing how to connect various components, and usage of Master, Slave and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
