OpenCores Wishbone B3 Synthesizable IP provides a smart way to verify the OpenCores Wishbone B3 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's OpenCores Wishbone B3 Synthesizable IP is fully compliant with standard OpenCores Wishbone B3 Specification and provides the following features
- Features
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- Compliant to OpenCores Wishbone B3 Protocol
- Support for all types of Wishbone devices
- Supports programmable wait states
- Supports programmable Retry insertion
- Supports programmable Error insertion
- Supports configurable transfer size for read and write transactions
- Supports linear,Fixed and Wrap burst sizes
- Supports flexibility to send completely configured data
- Ability to inject errors during data transfer
- Supports on-the-fly protocol and data checking
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- OpenCores Wishbone B3 Synthesizable Transactor Env
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SmartDV's OpenCores Wishbone B3 Synthesizable env contains following:
- Synthesizable transactors
- Complete regression suite containing all the OpenCores Wishbone B3 testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all class, task and functions used in verification env
- Documentation contains User's Guide and Release notes
