SafeSPI is the serial synchronous communication protocol based Flash VIP, supporting all major SafeSPI vendors. SafeSPI Verification IP can be used to verify SafeSPI Master or Slave in SOC. It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.
SafeSPI Verification IP
is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
SafeSPI Verification IP
comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
-
- Supports 100% of SafeSPI protocol Standards.
- Supports bit encodings
- Supports all SPI Transfers as per the Specification
- Supports all SafeSPI Timing Standards.
- Supports in-frame and out-of-frame communication
- Supports CRC calculation for in-frame and out-of-frame command/response.
- Supports backdoor access for memory and registers
- Built in functional coverage analysis.
- Supports Callbacks in master, slave and monitor for modifying, and sampling data/cmd on SafeSPI bus.
- SafeSPI Slave can be configured as standard device or can use FIFO for data passing.
- Master contains rich set of commands for both standard device and FIFO model mode.
- Notifies the test bench of significant events such as transactions, warnings, and protocol violations. This can be written to separate log files.
- SafeSPI Verification IP comes with complete test suite to test every feature of SafeSPI specification.
- Benefits
-
- Faster testbench development and more complete verification of SafeSPI designs.
- Easy to use command interface simplifies testbench control and configuration of slave and master.
- Simplifies results analysis.
- Runs in every major simulation environment
- SafeSPI Verification Env
-
SmartDV's SafeSPI Verification env contains following.
- Complete regression suite containing all the SafeSPI testcases.
- Examples showing how to connect various components, and usage of Master, Slave and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation contains User's Guide and Release notes.
