VC1 Decoder core is compliant with VC-1 standard specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices.VC1 Decoder is proven in FPGA environment. The host interface of the VC1 can be simple interface or can be AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
VC1 DECODER IIP is supported natively in Verilog and VHDL
- Features
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- Supports VC-1 standard specification.
- Supports full VC-1 encoder functionality.
- Supports video resolution up to 1920x1080@60fps.
- Supports Chroma type 4:4:4, 4:2:2 and 4:2:0.
- Supports variable size transform.
- Supports overlap transform and loop filtering.
- Supports baseline intra frame compression.
- Supports sequence level metadata
- Supports intensity compensation.
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to Microprocessor/Microcontroller devices
- Benefits
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- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's VC1 Decoder IP contains following
- The VC1 Decoder interface is available in Source and netlist products.
- The Source product is delivered in plain text verilog. If needed VHDL,SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
