LPSDR Synthesizable Transactor provides a smart way to verify the LPSDR component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's LPSDR Synthesizable Transactor is fully compliant with standard LPSDR Specification and provides the following features.
- Features
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- Supports 100% of LPSDR protocol standard LPSDR specification
- Supports all the LPSDR commands as per the LPSDR specification
- Supports following device density:
- Supports following device modes:
- Supports programmable burst lengths: 1, 2, 4, 8, and continuous
- Supports following burst type:
- Supports deep power down mode
- Supports auto-refresh and self-refresh mode
- Supports programmable partial array self refresh
- Supports burst termination operation
- Supports all data rates as per specification
- Checks for following:
- Check-points include power up, initialization and power off rules
- State based rules, active command rules
- Read/write command rules etc
- All timing violations
- Supports all mode registers programming
- Supports power down features
- Protocol checker fully compliant with LPSDR specification
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- LPSDR Synthesizable Transactor Env
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SmartDV's LPSDR Synthesizable Transactor env contains following:
- Synthesizable transactors
- Complete regression suite containing all the LPSDR testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes
