TDM Synthesizable Transactor provides a smart way to verify the TDM bi-directional two-wire bus component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's TDM Synthesizable Transactor is fully compliant with TDM blocks in IC's CS5368 , TMS320C642x and provides the following features.
- Features
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- Full TDM Transmitter, Receiver and Controller functionality
- Supports up to 32 channels in transmit path
- Supports up to 32 channels in receive path
- Supports programmable word length 8,12,16,20,24,32
- Supports programmable padding
- Supports programmable bit reversal
- Supports left and right justified
- Both transmitter and receiver can either work with SCK as input or can drive SCK
- Supports programmable data rate on transmit path
- Ability to detect and insert various types of error
- Can operate as master or slave in several configurations
- Master or slave mode as transmitter
- Master or slave mode as receiver
- Master mode as controller (does not transmit or receive data)
- The model has a rich set of configuration parameters to control TDM functionality
- Supports fully synthesizable
- Supports static synchronous design
- Supports positive edge clocking and no internal tri-states
- Supports simple interface allows easy connection to microprocessor/microcontroller devices
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- TDM Synthesizable Transactor Env
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SmartDV's TDM Synthesizable env contains following:
- Synthesizable transactors
- Complete regression suite containing all the TDM testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation contains User's Guide and Release notes
