RLDRAM3 Memory Model provides an smart way to verify the RLDRAM3 component of a SOC or a ASIC. The SmartDV's RLDRAM3 memory model is fully compliant with standard RLDRAM3 Specification and provides the following features. Better than Denali Memory Models.
RLDRAM3 Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
RLDRAM3 Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Supports RLDRAM3 memory devices from all leading vendors.
- Supports 100% of RLDRAM3 protocol standard.
- Supports all the RLDRAM3 commands as per the specs.
- Supports the following devices.
- Supports for SDR addressing.
- Supports Reduce cycle time (tRC(MIN) = 6.67 - 8ns).
- Supports Programmable READ/WRITE latency (RL/WL) and burst length.
- Supports Data mask for WRITE commands.
- Supports Integrated on-die termination (ODT).
- Supports Single or multibank writes.
- Supports Extended Operating range (200-1200MHZ).
- Supports READ training register.
- Supports Multiplexed and non-multiplexed addressing capabilities.
- Supports Mirror function.
- Supports Output driver and ODT calibration.
- Supports IEEE 1149.1 compliant JTAG boundary scan.
- Supports full-timing as well as behavioral versions in one model.
- Supports for all timing delay ranges in one model: min, typical and max.
- Protocol checker fully compliant with RLDRAM3 Specification.
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timings and protocol violations.
- Constantly monitors RLDRAM3 behavior during simulation.
- Built in functional coverage analysis.
- Supports Callbacks, so that user can access the data observed by monitor.
- Benefits
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- Faster testbench development and more complete verification of RLDRAM3 designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
- RLDRAM3 Verification Env
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SmartDV's RLDRAM3 Verification env contains following.
- Complete regression suite containing all the RLDRAM3 testcases.
- Examples showing how to connect and usage of Model.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
