AMBA ACE5-Lite Assertion IP provides an smart way to verify the ARM AMBA ACE5-Lite component of a SOC or a ASIC. The SmartDV's AMBA ACE5-Lite Assertion IP is fully compliant with standard AMBA ACE5-Lite Specification and provides the following features.
AMBA ACE5-Lite Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
AMBA ACE5-Lite Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Specification Compliance
- Compliant with the latest ARM AMBA ACE5-Lite Protocol Specification.
- Supports all ACE5-Lite data and address widths.
- Supports all protocol transfer types, burst types, burst lengths and response types.
- Separate address, data and response phases. Separate read and write channels.
- Support for burst-based transactions with only start address issued.
- Write strobe support.
- Narrow transfer support.
- Unaligned address access support.
- Ability to issue multiple outstanding transactions.
- Out of order transaction completion support.
- Protected accesses with normal/privileged, secure/non-secure and data/instruction.
- Ability to configure the width of all signals.
- Support for bus inactivity detection and timeout.
- Configurable WID signal enable support.
- Read data interleaving support with programmable interleave depth and programmable interleave size per transaction to allow fixed and variable data interleaving in a transaction.
- Atomic access support with normal access and exclusive access
- Longer bursts up to 256 beats.
- Quality of Service signaling.
- Multiple region interfaces.
- User signaling support.
- Ability to break longer bursts into multiple shorter bursts
- Supports unmapped region address accesses
- AWCACHE and ARCACHE Attributes.
- ACE-Lite specific features
- Supports functionality to verify ACE-Lite.
- Supports all ACE-Lite transaction types.
- Support for multiple outstanding ACE-Lite transactions.
- Supports all write/read responses.
- Shareable and Non-shareable transactions.
- Broadcast cache maintenance operations.
- ACE5-Lite specific features
- Atomic Transactions
- Cache Stash Transactions
- Deallocating Transactions
- CMO for Persistence
- Data Check
- Poison
- QoS Accept
- Trace signals
- User Loopback
- Wakeup signals
- Untranslated Transactions
- Non-secure Access Identifiers
- ACE5Lite-DVM specific features
- Atomic Transactions
- DVM v8.1
- Cache Stash Transactions
- Deallocating Transactions
- CMO for Persistence
- Data checking
- Poison
- QoS Accept
- Trace signals
- User Loopback
- Wakeup signals
- Coherency connection signals
- Untranslated Transactions
- Non-secure Access Identifiers
- ACE5-LiteACP specific features
- Data width and burst size upto 128 bits
- Burst length 1 or 4 beats
- Cache Stash Transactions
- Wakeup signals
- Data Check
- Poison
- Trace signals
- Assertion IP features
- Assertion IP includes:
- System Verilog assertions
- System Verilog assumptions
- System Verilog cover properties
- Synthesizable Verilog Auxiliary code
- Support Master mode, Slave mode, Monitor mode and Constraint mode.
- Supports Simulation mode (stimulus from SmartDV ACE5-Lite VIP) and Formal mode (stimulus from Formal tool).
- Rich set of parameters to configure ACE5-Lite Assertion IP functionality.
- Benefits
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- Runs in every major formal and simulation environment.
- AMBA ACE5-Lite Assertion Env
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SmartDV's AMBA ACE5-Lite Assertion env contains following.
- Detailed documentation of Assertion IP usage.
- Documentation also contains User's Guide and Release notes.
