MIPI DSI-2 Receiver interface provides full support for the two-wire MIPI DSI-2 Receiver synchronous serial interface, compatible with MIPI DSI and MIPI DSI 2 Specification version 1.3. Through its MIPI DSI-2 Receiver compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI DSI-2 Receiver IIP is proven in FPGA environment.The host interface of the MIPI DSI-2 Receiver can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
MIPI DSI-2 Receiver IIP is supported natively in Verilog and VHDL
- Features
-
- Compliant with MIPI DSI-2 specification v1.3
- Compliant with D - PHY Specification v1.1,v1.2,v2.0,v2.1
- Compliant with C - PHY Specification v0.7,v1.2
- Compliant with Display Pixel Interface (DPI -2) v 2.0
- Compliant with Display Bus Interface (DBI) v 2.0
- Compliant with Display Command Set (DCS) v 1.3
- Supports full MIPI DSI-2 Receiver functionality supporting CPHY and DPHY
- Supports Multi lane merging and also lanes can be configured up to 4 lanes for C - PHY and 4 lanes for D - PHY
- Supports Data rate up to 4.5 Gbps per data lane of D – PHY. 18 Gbps in 4 Lanes
- Supports Data rate up to 3 Gsps per trio using C – PHY. 17 Gbps in 3 Trios
- Supports up to 4 Virtual channels
- Supports PPI interface to connect to C - PHY / D – PHY
- Supports all types of Short and Long packets
- Supports all Virtual channel identifier
- Supports both Video and Command modes
- Supports Multiple packets per transmission
- Supports Deskew mechanism
- Supports 1-bit Error Correction and 2 bit Error Detection using ECC (6bit) for Packet header
- Supports Error Detection techniques for active data using Checksum(16 bit)
- Interrupt support for indicating internal status and error information
- Supports Sync event payloads
- Supports Burst, Non-Burst, Pulse and Event mode transfer over DPI Interface
- Supports Generic read / write over DBI Interface
- Supports display stream compression (DSC)
- Supports all BTA (Bi directional Turn around) commands
- Supports forward and reverse communication
- Supports both High speed and Low power packet reception
- Supports following formats
- YCbCr Data type - YCbCr422-20bit loosely packed pixel stream, YCbCr422-24bit packed pixel stream, YCbCr422-16bit packed pixel stream,YCbcr420-12bit packed pixel stream
- RGB Data type – RGB-30bit packed pixel stream, RGB565-16bit packed pixel stream, RGB666-18bit packed pixel stream, RGB888-24bit packed pixel stream, RGB666-18bit loosely packed pixel stream
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- Benefits
-
- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs,license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
-
SmartDV's MIPI DSI-2 Receiver IP contains following
- The MIPI DSI-2 Receiver interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
