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TDM Verification IP

TDM Verification IP

TDM Verification IP provides a smart way to verify TDM over I2S. The SmartDV's TDM Verification IP is compliant with TDM blocks in IC's CS5368 , TMS320C642x and provides the following features.

TDM Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

TDM Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Features
  • Full TDM Transmitter, Receiver and Controller functionality
  • Supports up to 32 channels in transmit path
  • Supports up to 32 channels in receive path
  • Supports programmable word length 8,12,16,20,24,32
  • Supports programmable padding
  • Supports programmable bit reversal
  • Supports left and right justified
  • Both transmitter and receiver can either work with SCK as input or can drive SCK
  • Supports programmable data rate on transmit path
  • Can operate as master or slave in several configurations
    • Master or slave mode as transmitter
    • Master or slave mode as receiver
    • Master mode as controller (does not transmit or receive data)
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Status counters for various events on bus.
  • Callbacks in transmitter, receiver and monitor for various events.
  • Supports constraints Randomization.
  • Built in functional coverage analysis.
Benefits
  • Faster testbench development and more complete verification of TDM designs.
  • Easy to use command interface simplifies testbench control and configuration of master and slave.
  • Simplifies results analysis.
  • Runs in every major simulation environment.
TDM Verification Env

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    SmartDV's TDM Verification env contains following.

  • Complete regression suite containing all the TDM testcases.
  • Examples showing how to connect various components, and usage of Master, Slave and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

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