PVCI Synthesizable Transactor provides a smart way to verify the PVCI component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's PVCI Synthesizable Transactor is fully compliant with standard PVCI Specification and provides the following features
- Features
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- Compliant to PVCI Protocol version 2.0
- Supports PVCI Initiator, PVCI Target
- Supports all PVCI data and address widths
- Supports 8-bit, 16-bit and 32-bit devices
- Supports 8-bit, 16-bit and 32-bit transfers
- Supports simple packet and burst transfer
- Supports Optional Free-BE mode
- Target supports fine grain control of response per address or per transfer
- Supports programmable wait state and timeout insertion
- Supports ability to inject errors during transfers
- Supports configurable PVCI interface size for read and write transfers
- Supports flexibility to send completely configured data
- Supports FIFO memory
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- PVCI Synthesizable Transactor Env
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SmartDV's PVCI Synthesizable env contains following
- Synthesizable transactors
- Complete regression suite containing all the PVCI testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all class, task and functions used in verification env
- Documentation contains User's Guide and Release notes
