The Ethercat Synthesizable Transactor is compliant with V1.0.3 specifications and verifies Ethercat interfaces. EtherCAT is build on top of it to make it robust. EtherCAT Synthesizable Transactor provides a smart way to verify the Ethercat component of a SOC or a ASIC in Emulator or FPGA platform. Ethercat Synthesizable Transactor is developed by experts in networking, who have developed networking products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a networking product.
- Features
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- Supports ETG.1000 S(R) V1.0.3 specification
- Supports Low Voltage Differential signaling interface
- Supports MII, MDIO RMII and RGMII Interface as per the ISO/IEC 8802-3 specification
- Supports RMII and RGMII Interface
- Supports Manchester Biphase L encoding and decoding
- Supports EtherCAT frame inside an Ethernet frame
- Supports EtherCAT frame inside an UDP datagram
- Supports all types of EtherCAT frames
- Supports full duplex mode of operation
- Supports clause22 and clause45
- Supports all types of TX and RX errors insertion/detection at each layer
- Supports Under and oversize frame
- Supports CRC errors
- Supports Framing errors
- Supports conformance tests as per ETG.7000.2 V1.0.6 specification
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- Ethercat Synthesizable Transactor Env
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SmartDV's Ethercat Synthesizable env contains following:
- Synthesizable transactors
- Complete regression suite containing all the Ethercat testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation contains User's Guide and Release notes
