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Products

AMBA ACE4 Verification IP

AMBA ACE4 Verification IP

AMBA ACE4 Verification IP provides an smart way to verify the ARM AMBA ACE4 component of a SOC or a ASIC. The SmartDV's AMBA ACE4 Verification IP is fully compliant with standard AMBA ACE4 Specification.

AMBA ACE4 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

AMBA ACE4 Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Features
  • Compliant with the latest ARM AMBA ACE4 Protocol Specification.
  • Supports ACE4 Master, Slave, Interconnect, Monitor and Checker.
  • Supports all ARM AMBA ACE4 data and address widths.
  • Supports all protocol transfer types, burst types, burst lengths, burst sizes and response types.
  • Supports constrained randomization of protocol attributes.
  • Separate address/control, data and response phases. Separate read, write and snoop channels.
  • Support for burst-based transactions with only start address issued.
  • Slave, Interconnect and Master support fine grain control of response per address or per transaction.
  • Programmable wait states or delay insertion on different channels. Interconnect has the ability to replicate Master/Slave inserted delays.
  • Ability to inject errors during data transfer.
  • Write strobe support to enable sparse data transfer on the write data bus.
  • Narrow transfer support.
  • Unaligned address access support.
  • Ability to issue multiple outstanding transactions.
  • Out of order transaction completion support.
  • Protected accesses with normal/privileged,secure/non-secure and data/instruction
  • Ability to configure the width of all signals.
  • Support for bus inactivity detection and timeout.
  • Configurable WID signal enable support.
  • Read data interleaving support with programmable interleave depth and programmable interleave size per transaction to allow fixed and variable data interleaving in a transaction.
  • Atomic access support with normal access and exclusive access
  • Longer bursts up to 256 beats.
  • Quality of Service signaling.
  • Multiple region interfaces.
  • User signaling support.
  • Ability to break longer bursts into multiple shorter bursts
  • Supports unmapped region address accesses
  • AWCACHE and ARCACHE Attributes.
  • Low-power Interface support
  • ACE4 specific features
    • Supports functionality to verify ACE4 and Cache Coherent Interconnect functionality for cache.
    • Supports all ACE4 transaction types including Snoop, Evict, WriteEvict, Barrier and Distributed virtual memory (DVM) transactions.
    • Support for multiple outstanding ACE4 transactions.
    • Supports all write/read responses and snoop responses.
    • Support for cache model and snoop filtering
    • Fine grain control of Initiating Master transaction including main memory access.
    • Fine grain control of Interconnect generated snoop transaction to snooped Masters.
    • Fine grain control of Interconnect generated main memory access transactions.
    • Fine grain control of Snooped Master’s response to a snoop transaction.
  • Programmable Timeout insertion.
  • Supports FIFO memory.
  • Rich set of configuration parameters to control ACE4 functionality.
  • On-the-fly protocol and data checking.
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in coverage analysis.
  • Callbacks in Master, Slave, Interconnect and Monitor for various events.
  • Status counters for various events on bus.
  • ACE4 Verification IP comes with complete testsuite to test every feature of ARM AMBA ACE4 specification.
Benefits
  • Faster testbench development and more complete verification of AMBA ACE4 designs.
  • Easy to use command interface simplifies testbench control and configuration of Master, Slave and Interconnect.
  • Simplifies results analysis.
  • Runs in every major simulation environment.
AMBA ACE4 Verification Env

    Note: Only mails from offical mail ID will be processed

    Request Datasheet
    Request Evaluation

    SmartDV's AMBA ACE4 Verification env contains following.

  • Complete regression suite containing all the AMBA ACE4 testcases.
  • Examples showing how to connect various components, and usage of BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

AMBA ACE5-Lite Verification IP

AMBA ACE5-Lite Verification IP

AMBA ACE5-Lite Verification IP provides an smart way to verify the ARM AMBA ACE5-Lite component of a SOC or a ASIC. The SmartDV's AMBA ACE5-Lite Verification IP is fully compliant with standard AMBA ACE5-Lite Specification.

AMBA ACE5-Lite Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

AMBA ACE5-Lite Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Features
  • Compliant with the latest ARM AMBA ACE5-Lite Protocol Specification.
  • Supports ACE5-Lite Master, Slave, Interconnect, Monitor and Checker.
  • Supports all ARM AMBA ACE5-Lite data and address widths.
  • Supports all protocol transfer types, burst types, burst lengths and response types.
  • Supports constrained randomization of protocol attributes.
  • Separate address/control, data and response phases. Separate read and write channels.
  • Support for burst-based transactions with only start address issued.
  • Slave, Interconnect and Master support fine grain control of response per address or per transaction.
  • Programmable wait states or delay insertion on different channels. Interconnect has the ability to replicate Master/Slave inserted delays.
  • Ability to inject errors during data transfer.
  • Write strobe support to enable sparse data transfer on the write data bus.
  • Narrow transfer support.
  • Unaligned address access support.
  • Ability to issue multiple outstanding transactions.
  • Out of order transaction completion support.
  • Protected accesses with normal/privileged,secure/non-secure and data/instruction
  • Ability to configure the width of all signals.
  • Support for conversion of different protocols and different data width.
  • Support for bus inactivity detection and timeout.
  • Configurable WID signal enable support.
  • Read data interleaving support with programmable interleave depth and programmable interleave size per transaction to allow fixed and variable data interleaving in a transaction.
  • Atomic access support with normal access and exclusive access
  • Longer bursts up to 256 beats.
  • Quality of Service signaling.
  • Multiple region interfaces.
  • User signaling support.
  • Ability to break longer bursts into multiple shorter bursts
  • Supports unmapped region address accesses
  • AWCACHE and ARCACHE Attributes.
  • Low-power Interface support
  • ACE-Lite specific features
    • Supports functionality to verify ACE-Lite.
    • Supports all ACE-Lite transaction types.
    • Support for multiple outstanding ACE-Lite transactions.
    • Supports all write/read responses.
    • Fine grain control of Initiating Master transaction including main memory access.
    • Fine grain control of Interconnect generated main memory access transactions.
    • Shareable and Non-shareable transactions.
    • Broadcast cache maintenance operations.
  • ACE5-Lite specific features
    • Atomic Transactions
    • Cache Stash Transactions
    • Deallocating Transactions
    • CMO for Persistence
    • Data Check
    • Poison
    • QoS Accept
    • Trace signals
    • User Loopback
    • Wakeup signals
    • Untranslated Transactions
    • Non-secure Access Identifiers
  • ACE5Lite-DVM specific features
    • Atomic Transactions
    • DVM v8.1
    • Cache Stash Transactions
    • Deallocating Transactions
    • CMO for Persistence
    • Data checking
    • Poison
    • QoS Accept
    • Trace signals
    • User Loopback
    • Wakeup signals
    • Coherency connection signals
    • Untranslated Transactions
    • Non-secure Access Identifiers
  • ACE5-LiteACP specific features
    • Data width and burst size upto 128 bits
    • Burst length 1 or 4 beats
    • Cache Stash Transactions
    • Wakeup signals
    • Data Check
    • Poison
    • Trace signals
  • Programmable Timeout insertion.
  • Supports FIFO memory.
  • Rich set of configuration parameters to control ACE5-Lite functionality.
  • On-the-fly protocol and data checking.
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in coverage analysis.
  • Callbacks in Master, Slave, Interconnect and Monitor for various events.
  • Status counters for various events on bus.
  • ACE5-Lite Verification IP comes with complete testsuite to test every feature of ARM AMBA ACE5-Lite specification.
Benefits
  • Faster testbench development and more complete verification of AMBA ACE5-Lite designs.
  • Easy to use command interface simplifies testbench control and configuration of Master, Slave and Interconnect.
  • Simplifies results analysis.
  • Runs in every major simulation environment.
AMBA ACE4 Verification Env

    Note: Only mails from offical mail ID will be processed

    Request Datasheet
    Request Evaluation

    SmartDV's AMBA ACE4 Verification env contains following.

  • Complete regression suite containing all the AMBA ACE4 testcases.
  • Examples showing how to connect various components, and usage of BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.
  • AMBA ACE5-Lite Verification Env
  • SmartDV's AMBA ACE5-Lite Verification env contains following.
  • Complete regression suite containing all the AMBA ACE5-Lite testcases.
  • Examples showing how to connect various components, and usage of BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

AMBA ACE5 Verification IP

AMBA ACE5 Verification IP

AMBA ACE5 Verification IP provides an smart way to verify the ARM AMBA ACE5 component of a SOC or a ASIC. The SmartDV's AMBA ACE5 Verification IP is fully compliant with standard AMBA ACE5 Specification.

AMBA ACE5 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

AMBA ACE5 Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Features
  • Compliant with the latest ARM AMBA ACE5 Protocol Specification.
  • Supports ACE5 Master, Slave, Interconnect, Monitor and Checker.
  • Supports all ARM AMBA ACE5 data and address widths.
  • Supports all protocol transfer types, burst types, burst lengths and response types.
  • Supports constrained randomization of protocol attributes.
  • Separate address/control, data and response phases. Separate read, write and snoop channels.
  • Support for burst-based transactions with only start address issued.
  • Slave, Interconnect and Master support fine grain control of response per address or per transaction.
  • Programmable wait states or delay insertion on different channels. Interconnect has the ability to replicate Master/Slave inserted delays.
  • Ability to inject errors during data transfer.
  • Write strobe support to enable sparse data transfer on the write data bus.
  • Narrow transfer support.
  • Unaligned address access support.
  • Ability to issue multiple outstanding transactions.
  • Out of order transaction completion support.
  • Protected accesses with normal/privileged,secure/non-secure and data/instruction
  • Ability to configure the width of all signals.
  • Support for conversion of different protocols and different data width.
  • Support for bus inactivity detection and timeout.
  • Configurable WID signal enable support.
  • Read data interleaving support with programmable interleave depth and programmable interleave size per transaction to allow fixed and variable data interleaving in a transaction.
  • Atomic access support with normal access and exclusive access
  • Longer bursts up to 256 beats.
  • Quality of Service signaling.
  • Multiple region interfaces.
  • User signaling support.
  • Ability to break longer bursts into multiple shorter bursts
  • Supports unmapped region address accesses
  • AWCACHE and ARCACHE Attributes.
  • Low-power Interface support
  • ACE specific features
    • Supports functionality to verify ACE and Cache Coherent Interconnect functionality for cache.
    • Supports all ACE transaction types including Snoop, Evict, WriteEvict and Distributed virtual memory (DVM) transactions.
    • Support for multiple outstanding ACE transactions.
    • Supports all write/read responses and snoop responses.
    • Support for cache model and snoop filtering
    • Fine grain control of Initiating Master transaction including main memory access.
    • Fine grain control of Interconnect generated snoop transaction to snooped Masters.
    • Fine grain control of Interconnect generated main memory access transactions.
    • Fine grain control of Snooped Master’s response to a snoop transaction.
  • ACE5 specific features
    • DVM v8.1
    • CMO for Persistence
    • Data Check
    • Poison
    • QoS Accept
    • Trace signals
    • User Loopback
    • Wakeup signals
    • Coherency connection signals
    • Untranslated transactions
    • Non-Secure Access Identifiers
  • Programmable Timeout insertion.
  • Supports FIFO memory.
  • Rich set of configuration parameters to control ACE5 functionality.
  • On-the-fly protocol and data checking.
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in coverage analysis.
  • Callbacks in Master, Slave, Interconnect and Monitor for various events.
  • Status counters for various events on bus.
  • ACE5 Verification IP comes with complete testsuite to test every feature of ARM AMBA ACE5 specification.
Benefits
  • Faster testbench development and more complete verification of AMBA ACE5 designs.
  • Easy to use command interface simplifies testbench control and configuration of Master, Slave and Interconnect.
  • Simplifies results analysis.
  • Runs in every major simulation environment.
AMBA ACE4 Verification Env

    Note: Only mails from offical mail ID will be processed

    Request Datasheet
    Request Evaluation

    SmartDV's AMBA ACE4 Verification env contains following.

  • Complete regression suite containing all the AMBA ACE4 testcases.
  • Examples showing how to connect various components, and usage of BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.
  • AMBA ACE5-Lite Verification Env
  • SmartDV's AMBA ACE5-Lite Verification env contains following.
  • Complete regression suite containing all the AMBA ACE5-Lite testcases.
  • Examples showing how to connect various components, and usage of BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.
  • AMBA ACE5 Verification Env
  • SmartDV's AMBA ACE5 Verification env contains following.
  • Complete regression suite containing all the AMBA ACE5 testcases.
  • Examples showing how to connect various components, and usage of BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

AMBA ACE4-Lite Verification IP

AMBA ACE4-Lite Verification IP

AMBA ACE4-Lite Verification IP provides an smart way to verify the ARM AMBA ACE4-Lite component of a SOC or a ASIC. The SmartDV's AMBA ACE4-Lite Verification IP is fully compliant with standard AMBA ACE4-Lite Specification.

AMBA ACE4-Lite Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

AMBA ACE4-Lite Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Features
  • Compliant with the latest ARM AMBA ACE4-Lite Protocol Specification.
  • Supports ACE4-Lite Master, Slave, Interconnect, Monitor and Checker.
  • Supports all ACE4-Lite data and address widths.
  • Supports all protocol transfer types, burst types, burst lengths, burst sizes and response types.
  • Supports constrained randomization of protocol attributes.
  • Separate address/control, data and response phases. Separate read and write channels.
  • Support for burst-based transactions with only start address issued.
  • Slave, Interconnect and Master support fine grain control of response per address or per transaction.
  • Programmable wait states or delay insertion on different channels. Interconnect has the ability to replicate Master/Slave inserted delays.
  • Ability to inject errors during data transfer.
  • Write strobe support to enable sparse data transfer on the write data bus.
  • Narrow transfer support.
  • Unaligned address access support.
  • Ability to issue multiple outstanding transactions.
  • Out of order transaction completion support.
  • Protected accesses with normal/privileged,secure/non-secure and data/instruction
  • Ability to configure the width of all signals.
  • Support for conversion of different protocols and different data width.
  • Support for bus inactivity detection and timeout.
  • Configurable WID signal enable support.
  • Read data interleaving support with programmable interleave depth and programmable interleave size per transaction to allow fixed and variable data interleaving in a transaction.
  • Atomic access support with normal access and exclusive access
  • Longer bursts up to 256 beats.
  • Quality of Service signaling.
  • Multiple region interfaces.
  • User signaling support.
  • Ability to break longer bursts into multiple shorter bursts
  • Supports unmapped region address accesses
  • AWCACHE and ARCACHE Attributes.
  • Low-power Interface support
  • ACE4-Lite specific features
    • Supports functionality to verify ACE4-Lite.
    • Supports all ACE4-Lite transaction types.
    • Support for multiple outstanding ACE4-Lite transactions.
    • Supports all write/read responses.
    • Fine grain control of Initiating Master transaction including main memory access.
    • Fine grain control of Interconnect generated main memory access transactions.
    • Barrier transactions
    • Shareable and Non-shareable transactions.
    • Broadcast cache maintenance operations.
  • Programmable Timeout insertion.
  • Supports FIFO memory.
  • Rich set of configuration parameters to control ACE4-Lite functionality.
  • On-the-fly protocol and data checking.
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in coverage analysis.
  • Callbacks in Master, Slave, Interconnect and Monitor for various events.
  • Status counters for various events on bus.
  • ACE4-Lite Verification IP comes with complete testsuite to test every feature of ARM AMBA ACE4-Lite specification.
Benefits
  • Faster testbench development and more complete verification of AMBA ACE4-Lite designs.
  • Easy to use command interface simplifies testbench control and configuration of Master, Slave and Interconnect.
  • Simplifies results analysis.
  • Runs in every major simulation environment.
AMBA ACE4 Verification Env

    Note: Only mails from offical mail ID will be processed

    Request Datasheet
    Request Evaluation

    SmartDV's AMBA ACE4 Verification env contains following.

  • Complete regression suite containing all the AMBA ACE4 testcases.
  • Examples showing how to connect various components, and usage of BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.
  • AMBA ACE5-Lite Verification Env
  • SmartDV's AMBA ACE5-Lite Verification env contains following.
  • Complete regression suite containing all the AMBA ACE5-Lite testcases.
  • Examples showing how to connect various components, and usage of BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.
  • AMBA ACE5 Verification Env
  • SmartDV's AMBA ACE5 Verification env contains following.
  • Complete regression suite containing all the AMBA ACE5 testcases.
  • Examples showing how to connect various components, and usage of BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.
  • AMBA ACE4-Lite Verification Env
  • SmartDV's AMBA ACE4-Lite Verification env contains following.
  • Complete regression suite containing all the AMBA ACE4-Lite testcases.
  • Examples showing how to connect various components, and usage of BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

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