FCRAM Synthesizable Transactor provides a smart way to verify the FCRAM component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's FCRAM Synthesizable Transactor is fully compliant with standard FCRAM Specification and provides the following features.
- Features
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- Supports 100% of FCRAM protocol standard FCRAM specifications
- Supports all the FCRAM commands as per the specs
- Supports up to 512MB device density
- Supports up to four internal banks
- Supports programmable write latency
- Supports programmable burst lengths:
- Supports sequential burst type
- Supports burst order
- Supports all mode registers programming
- Checks for following:
- Check-points include power on, initialization and power off rules
- State based rules, active command rules
- Read/Write command rules etc
- All timing violations
- Supports self refresh, power down and deep power down operation
- Supports auto refresh operation
- Supports additional RDQS toggle (ART)
- Supports write data mask and data strobe features
- Supports background refresh and burst terminate operations
- Supports clock stop capability during idle periods
- Supports both synchronous and asynchronous on-die termination modes
- Supports all types of timing and protocol violation detection
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- FCRAM Synthesizable Transactor Env
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SmartDV's FCRAM Synthesizable Transactor env contains following:
- Synthesizable transactors
- Complete regression suite containing all the FCRAM testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes
