Real Time Clock is used to generate precise time, date, alarm pulse after programmed period and keeps track of events, compatible with standard protocol of RTC specification. Through its RTC compatibility, it provides a simple interface to a wide range of low-cost devices. RTC IIP is proven in FPGA environment.The host interface of the RTC can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
RTC IIP is supported natively in Verilog and VHDL
- Features
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- Supports to generate alarm interrupt after a time period
- Supports to generate seconds, minutes and hours value
- Supports configurable seconds, minutes and hours value
- Supports calendaring functionality
- Supports clock timer functionality
- Supports up and down timer counting modes
- Supports to hold count value.
- Supports enabling and disabling of interrupts.
- Fully synthesizable.
- Static synchronous design.
- Positive edge clocking and no internal tri-states.
- Scan test ready.
- Simple interface allows easy connection to microprocessor/microcontroller devices.
- Benefits
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- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's RTC IP contains following
- The RTC interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
