MIPI DPHY Synthesizable VIP provides a smart way to verify the MIPI DPHY component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's MIPI DPHY Synthesizable VIP is fully compliant with standard 2.1 MIPI DPHY Specifications and provides the following features.
- Features
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- Supports 2.1 MIPI DPHY Specifications
- Supports both serial and PPI functionality testing
- Supports full MIPI DPHY Transmitter and Receiver functionality
- Operates as a Transmitter,Receiver
- Supports short and long packets
- Supports BTA testing
- Supports all lane configuration
- Supports multiple packets per transmission
- Supports Skew Calibration
- Supports Alternate Calibration Sequence
- Supports Preamble Sequence
- Supports HS-Idle state in serial and PPI mode
- Supports differential and single ended mode of operation
- Supports various kind of Transmitter and Receiver errors generation and detection
- SoT Error
- SoT Sync Error
- EoT Sync Error
- Escape Entry Command Error
- LP Transmission Sync Error
- False Control Error
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- MIPI DPHY Synthesizable VIP Env
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SmartDV's MIPI DPHY Synthesizable VIP env contains following:
- Synthesizable transactors
- Complete regression suite containing all the MIPI DPHY testcases
- Examples showing how to connect various components, and usage of Synthesizable VIP
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation also contains User's Guide and Release notes
