MIPI CPHY Synthesizable VIP provides a smart way to verify the MIPI CPHY component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's MIPI CPHY Synthesizable VIP is fully compliant with standard MIPI CPHY Specification and provides the following features.
- Features
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- Supports MIPI CPHY Specifications
- Supports up to 32 trio lanes
- Supports both serial and PPI functionality testing
- Supports full MIPI CPHY Transmitter and Receiver functionality
- Operates as a Transmitter, Receiver
- Supports PRBS Pattern generation
- Supports short and long packets
- Supports BTA testing
- Supports to set symbol clock
- Supports to set lane skew between lanes in a trio for arrival of sot
- Supports all lane configuration
- Supports multiple packets per transmission
- Supports different SYNC word in serial and ppi
- Supports calibration preamble formats in serial
- Supports ALP mode in serial and ppi
- Supports differential and single ended mode of operation
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- MIPI CPHY Synthesizable VIP Env
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SmartDV's MIPI CPHY Synthesizable VIP env contains following:
- Synthesizable transactors
- Complete regression suite containing all the MIPI CPHY testcases
- Examples showing how to connect various components, and usage of Synthesizable VIP
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation also contains User's Guide and Release notes
