DDR PHY Interface(DFI) provides an smart way to verify the DFI component of a SOC or a ASIC. The SmartDV's DDR PHY Interface(DFI) is fully compliant with standard DFI Specification and provides the following features.
DFI Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
DFI Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Compliant with DFI version 2.0, 2.1, 3.0, 3.1, 4.0 and 5.0 Specifications.
- DFI Applies to :
- DDR5 protocol standard JESD79-5 Rev082 (Draft) Specification
- DDR4 protocol standard JESD79-4D (Draft) Specification
- DDR3 protocol standard JESD79-3F Specification
- LPDDR5 protocol standard JESD209-5 Specification
- LPDDR4 protocol standard JESD209-4B Specification
- LPDDR3 protocol standard JESD209-3C Specification
- Supports all Interface Groups.
- Supports Write Transactions with DBI, DM and CRC.
- Supports Read Transactions with DBI.
- Supports DRAM Clock disabling feature.
- Supports Data bit enable/disable feature.
- Supports 1:1, 1:2 and 1:4 MC to PHY frequency ratio.
- Supports frequency change protocol.
- Supports CA Parity Signaling.
- Supports Low power control features.
- Supports Error signaling.
- Supports Independent Operation & Multi-Configuration Support for LPDDR4.
- Supports DB Data Buffer Training.
- Supports Per-Slice Read Leveling.
- Supports CA Training.
- Supports DFI Read/Write Chip Select.
- Supports Write Leveling Strobe Update.
- Supports DDR WR DQ Training.
- Supports Gear down Mode(2N Mode).
- Supports 3D Stack.
- Supports Inactive CS.
- Supports WCK Control Interface for LPDDR5.
- Supports all types of timing and protocol violations detection for timing parameters like tphy_wrlat ,tphy_wrdata,trd_dataen and tphy_rdlat delays
- Constantly monitors DFI behavior during simulation.
- Protocol checker fully compliant with DFI 2.0, 2.1, 3.0, 3.1, 4.0 and 5.0 Specifications.
- Bus-accurate timing for min, max and typical values.
- Notifies the test bench of significant events such as transactions, warnings.
- Built in functional coverage analysis.
- Supports Callbacks, so that user can access the data observed by monitor.
- Benefits
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- Faster test bench development and more complete verification of DFI designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
- DFI Verification Env
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SmartDV's DFI Verification env contains following.
- Complete regression suite containing all the DFI testcases.
- Complete UVM/OVM sequence library for DFI controller.
- Examples showing how to connect and usage of Model.
- Detailed documentation of all classes, tasks and functions used in verification env.
- Documentation also contains User's Guide and Release notes.
