AMBA AXI3/AXI4/AXI4-Stream/AXI5/ACE/ACE5 Assertion IP provides an smart way to verify the ARM AMBA AXI3/AXI4/AXI4-Stream/AXI5/ACE/ACE5 component of a SOC or a ASIC. The SmartDV's AMBA AXI3/AXI4/AXI4-Stream/AXI5/ACE/ACE5 Assertion IP is fully compliant with standard ARM AMBA AXI3/AXI4/AXI4-Stream/AXI5/ACE/ACE5 Specification and provides the following features.
AMBA AXI3/AXI4/AXI4-Stream/AXI5/ACE/ACE5 AIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
AMBA AXI3/AXI4/AXI4-Stream/AXI5/ACE/ACE5 AIP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Specification Compliance
- Compliant with the latest ARM AMBA 5 AXI, ACE specification.
- Supports AXI Master, AXI Slave, AXI Monitor and AXI Checker.
- Supports all ARM AMBA AXI 3.0/4.0/5.0 data and address widths.
- Supports all protocol transfer types, burst types, burst lengths and response types.
- Support for burst-based transactions.
- AXI3/AXI4/AXI5/ACE/ACE5 Common support
- Write strobe support.
- Narrow transfer support.
- Unaligned address access support.
- Supports multiple outstanding transactions.
- Out of order transaction completion support.
- Protected accesses with normal/privileged,secure/non-secure and data/instruction
- Ability to configure the width of all signals.
- Support for bus inactivity detection and timeout.
- Configurable WID signal enable support for AXI4/ACE/ACE-Lite.
- AXI3 support
- Write data and read data interleaving support.
- Configurable write and read interleave depth.
- Programmable interleave size per transaction to allow fixed and variable data interleaving in a transaction.
- Low-power Interface support
- Atomic access support with normal access,exclusive access and locked access
- AXI4 support
- Read data interleaving support with programmable interleave depth and programmable interleave size per transaction to allow fixed and variable data interleaving in a transaction.
- Atomic access support with normal access and exclusive access
- Longer bursts up to 256 beats.
- Quality of Service signaling.
- Multiple region interfaces.
- User signaling support.
- Supports unmapped region address accesses
- AWCACHE and ARCACHE Attributes.
- Low-power Interface support
- AXI4-Lite support
- Burst length of 1.
- Write strobe support.
- Data bus width of 32-bit or 64-bit.
- Supports multiple outstanding transactions.
- ACE support
- In addition to AXI4 features, ACE supports the following features,
- Supports functionality to verify ACE and CCI interconnect functionality for cache.
- Supports all ACE transaction types including Snoop, Evict, WriteEvict, Barrier and Distributed virtual memory (DVM) transactions.
- Support for multiple outstanding ACE transactions.
- Supports all write/read responses and snoop responses.
- Support for cache model and snoop filtering
- ACE-Lite support
- Barrier transactions
- Shareable and Non-shareable transactions.
- Broadcast cache maintenance operations.
- AMBA5 support
- Supports Atomic transactions.
- Supports Cache stashing.
- Supports Deallocating transactions.
- Supports Cache Maintenance for persistence.
- Supports Data Checking and Poison.
- Supports Trace Signals.
- Supports for User Loopback Signaling.
- Supports Qos Accept signaling.
- Supports Wake-up Signaling mechanism.
- Supports Coherency Connection signaling
- Supports Distributed Virtual Memory extensions for ARMv8.1
- Supports Untranslated transactions
- Supports Non-secure access identifiers
- Assertion IP features
- AIP includes:
- System Verilog assertions
- System Verilog assumptions
- System Verilog cover properties
- Synthesizable Verilog Auxiliary code
- Support Master mode, Slave mode, Monitor mode and Constraint mode.
- Supports Simulation mode (stimulus from SmartDV AXI VIP) and Formal mode (stimulus from Formal tool).
- Rich set of parameters to configure AXI AIP functionality.
- Benefits
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- Runs in every major formal and simulation environment.
- AMBA AXI3/AXI4/AXI4-Stream/AXI5/ACE/ACE5 Assertion Env
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SmartDV's AMBA AXI3/AXI4/AXI4-Stream/AXI5/ACE/ACE5 Assertion env contains following.
- Detailed documentation of AIP usage.
- Documentation also contains User's Guide and Release notes.
