DFI Assertion IP provides an efficient and smart way to verify the DFI memory model quickly without a testbench. The SmartDV's DFI Assertion IP is fully compliant with standard DFI 2.x/3.0 Specification.
DFI AIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
DFI AIP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Specification Compliance
- Compliant to DFI 2.x/3.0 protocol
- Supports DFI Data Bit Disable
- Supports Geardown Mode
- Supports all types of timing and protocol violation detection.
- Supports Write Leveling Strobe Update.
- Checks for following
- Check-points include power on, Initialization and power off rules,
- State based rules, Active Command rules,
- Read/Write Command rules etc.
- Bus-accurate timing for min, max and typical values.
- Supports all types of timing and protocol violation detection.
- Supports Write Transactions with DBI and CRC
- Supports Read Transactions with DBI
- Supports 1:1, 1:2 and 1:4 MC to PHY frequency ratio
- Assertion IP features
- AIP includes:
- System Verilog assertions
- System Verilog assumptions
- System Verilog cover properties
- Synthesizable Verilog Auxiliary code
- Support Master mode, Slave mode, Monitor mode and Constraint mode.
- Supports Simulation mode (stimulus from SmartDV DFI VIP) and Formal mode (stimulus from Formal tool).
- Rich set of parameters to configure DFI AIP functionality.
- Benefits
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- Runs in every major formal and simulation environment.
- DFI Assertion Env
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SmartDV's DFI Assertion env contains following.
- Detailed documentation of AIP usage.
- Documentation also contains User's Guide and Release notes.
