I2S Master interface provides full support for the two-wire I2S synchronous serial interface, compatible with I2S specification. Through its I2S compatibility, it provides a simple interface to a wide range of low-cost devices. I2S Master IIP is proven in FPGA environment. The host interface of I2S can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
I2S Master Controller IIP is supported natively in Verilog and VHDL
- Features
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- Compliant with 1.0 I2S Specification
- Full I2S Transmit and Receiver functionality
- Supports upto 32 channels in transmit path
- Supports upto 32 channels in receive path
- Supports programmable word length 8,12,16,20,24,32
- Supports programmable padding
- Supports programmable bit rotate
- Supports programmable bit reversal
- Supports left and right justified
- Both transmitter and receiver can either work with SCK as input or can drive SCK
- Supports programmable data rate on transmit path
- All transmit channels controled from one set of configuraion registers
- All receive channels controled from one set of configuraion registers
- Fully Synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to Microprocessor/Microcontroller devices.
- Benefits
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- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's I2S Master IP contains following
- The I2S Master interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases.
- Lint, CDC, Synthesis, Simulation Scripts with waiver files.
- IP-XACT RDL generated address map.
- Firmware code and Linux driver package.
- Documentation contains User's Guide and Release notes.
