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DFI Synthesizable Memory Model

DFI Synthesizable Memory Model

DFI Synthesizable Memory Model provides a smart way to verify the DFI component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's DFI Synthesizable memory model is fully compliant with standard DFI 3.1 Specification and Preliminary DFI 4.0 Specification and provides the following features.

Features
  • Compliant with DFI version 2.0, 2.1, 3.0, 3.1, 4.0 and 5.0 Specifications
  • DFI Applies to :
    • DDR5 protocol standard JEDS79-5 Rev082 (Draft) Specification
    • DDR4 protocol standard JESD79-4D (draft) Specification
    • DDR3 protocol standard JESD79-3F Specification
    • LPDDR5 protocol standard JESD209-5 Specification
    • LPDDR4 protocol standard JESD209-4B Specification
    • LPDDR3 protocol standard JESD209-3C Specification
  • Supports all Interface Groups.
  • Supports Data Bus Inversion with write and read data transmissions
  • Supports Write Transactions with DBI and CRC
  • Supports Read Transactions with DBI
  • Supports DRAM Clock disabling feature
  • Supports Data bit enable/disable feature
  • Supports 1:1, 1:2 and 1:4 MC to PHY frequency ratio
  • Supports frequency change protocol
  • Supports CA Parity Signaling
  • Supports Low power control features
  • Supports Error signaling
  • Supports Independent channel Operation & Multi-Configuration Support for LPDDR4
  • Supports DB Data Buffer Training
  • Supports Per-Slice Read Leveling
  • Supports CA Training
  • Supports DFI Read/Write Chip Select
  • Supports Write Leveling Strobe Update
  • Supports DDR WR DQ Training
  • Supports DFI Data Byte Disable
  • Supports Gear down Mode(2N Mode)
  • Supports 3D Stack
  • Supports Inactive CS
  • Supports WCK Control Interface for LPDDR5
  • Supports all types of timing and protocol violation detection
  • Checks for following
    • Power on, Initialization and Power off rules
    • State based rules, Active Command rules
    • Read/Write Command rules
    • All timing violations
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timings and protocol violations
Benefits
  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms
DFI Synthesizable VIP Env

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    SmartDV's DFI Synthesizable VIP env contains following:

  • Synthesizable transactors
  • Complete regression suite containing all the DFI testcases
  • Examples showing how to connect various components, and usage of Synthesizable Memory model
  • Detailed documentation of all DPI, class, task and function's used in verification env
  • Documentation contains User's Guide and Release notes

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