MIPI DSI-2 TX interface provides full support for the two-wire MIPI DSI-2 TX synchronous serial interface, compatible with MIPI DSI and MIPI DSI 2 Specification version 3.1. Through its MIPI DSI-2 TX compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI DSI-2 TX IIP is proven in FPGAenvironment.The host interface of the MIPI DSI-2 TX can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Wishbone or Custom protocol.
MIPI DSI-2 TX IIP is supported natively in Verilog and VHDL
- Features
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- Compliant with MIPI DSI2 Specification v1.0, v1.2,v3.1
- Full MIPI DSI2 Transmitter core functionality.
- Supports two types of PHY layer.
- Supports Data rate in range of 80 Mbps to 1500Mbps in DPHY Lanes.
- Supports Data rate in range of 0.8 Gsps to 6Gsps in CPHY Lanes.
- Supports PPI interface.
- Supports all types of short packets and long packets
- Supports 1 to 4 lane configurations.
- Supports all virtual channel identifier.
- Supports both video and command modes.
- Supports bi directional low power data transmission(LPDT)
- Supports Serial Display Interface (SDI), MIPI Display Pixel Interface (DPI SM), and Display Compression (DSC) input interface options
- Connects to MIPI D-PHY lane modules through PPI up to 4 data lanes)
- Supports Programmable test video generator for integration debug and test
- 32-bit Arm AMBA 3 Advanced Peripheral Bus (APB) slave interface for register access
- Supports multiple packets per transmission.
- Supports sync event payloads.
- Supports display stream compression (DSC).
- Supports MIPI DSI-2 Specification.
- Supports MIPI DBI specification.
- Supports MIPI DCS specification.
- Supports all BTA commands.
- Supports Link Distribution Function.
- Supports both high speed and low power packet transmission and reception.
- Supports 1-bit error correction and 2 bit error detection using ECC (6 bit) for packet header.
- Supports error detection techniques for active data using checksum (16 bit).
- Supports the following pixel formats
- RGB data type
- 12 bit RGB 444 format
- 24 bit RGB 888 format
- 16 bit RGB 565 format
- 18 bit RGB 666 format
- YCbCr data type
- 20 bit YCbCr 4:2:2
- 24 bit YCbCr 4:2:2
- 16bit YCbCr 4:2:2
- 12 bit YCbCr 4:2:0
- Interrupt support for indicating internal status/error information.
- Fully synthesizable.
- Static synchronous design.
- Positive edge clocking and no internal tri-states.
- Scan test ready.
- Simple interface allows easy connection to microprocessor/microcontroller devices.
- Benefits
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- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- MIPI DSI-2 TX IP
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SmartDV's MIPI DSI-2 TX IP contains following
- The MIPI DSI-2 TX interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Integration testbench and tests.
- Scripts for simulation and synthesis with support for common EDA tools.
- Documentation contains User's Guide and Release notes.
