MIPI CSI-2 TX interface provides full support for the two-wire MIPI CSI2 serial interface, compatible with MIPI CSI 2 Bus Specification version 2.1. It is typically residing in a camera module and provides communication to MIPI CSI-2 receiver in an image application processor over the serial PHY link. MIPI CSI-2 TX IIP is fully configurable and proven in FPGA environment. The host interface of the MIPI CSI-2 can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Wishbone or Custom bus protocol.
MIPI CSI-2 TX IIP is supported natively in Verilog and VHDL
- Features
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- Compliant with MIPI CSI-2 Specification v1.0, v1.1, v1.3, v2.0,v2.1
- Compliant with D - PHY Specification v1.1,v1.2,v2.0,v2.1
- Compliant with C - PHY Specification v0.7,v1.2
- Full MIPI CSI-2 TRANSMITTER functionality where either D - PHY / C - PHY can be used
- Supports Multi lane distribution and also lanes can be configured up to 3 lanes for C - PHY and 8 lanes for D - PHY
- Supports Data rate in range 2.5 Gbps in DPHY Lanes.
- Supports Data rate in range of 0.8 Gsps to 6Gsps in CPHY Lanes.
- Supports PPI Interface to connect to C - PHY / D - PHY
- Supports Short and Long packets
- Supports Frame and Line Synchronization Packets (Short Packets)
- Supports Data Scrambling in Lanes.
- Supports High Speed and Escape Mode (LPDT and ULPS) Transmission.
- Supports various methods to interleave the transmission of different image data formats
- Data type
- Virtual channel
- Supports 1-bit Error Correction and 2-bit Error Detection using ECC (6 bit) for Packet Header.
- Supports Error Detection techniques for active data using Checksum (16 bit).
- Supports Image applications with varying Pixel formats
- RAW Data Type
- RGB Data Type
- YUV Data Type
- User Defined data type – 8-bit
- Generic 8-bit long packets (Null, Blanking, Embedded data)
- Multiple video formats with up to four pixels per pixel clock
- Supports Video Stream Interface at Pixel Level
- Interrupt support for indicating internal status/error information.
- Supports ALPS (Alternate Low Power State) in C- PHY mode.
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- Benefits
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- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- MIPI CSI-2 TX IP
-
SmartDV's MIPI CSI-2 TX IP contains following.
- The MIPI CSI-2 TX interface is available in Source and netlist products
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Integration testbench and tests
- Scripts for simulation and synthesis with support for common EDA tools
- Documentation contains User's Guide and Release notes.
