MIPI CSI-2 RX interface provides full support for the two-wire MIPI CSI2 serial interface, compatible with MIPI CSI 2 Bus Specification version 2.1. It is typically residing in an image application processor and provides communication to MIPI CSI-2 transmitter in a camera module over the serial PHY link. MIPI CSI-2 RX IIP is fully configurable and proven in FPGA environment. The host interface of the MIPI CSI-2 RX IP can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Wishbone or Custom bus protocol.
MIPI CSI-2 RX IIP is supported natively in Verilog and VHDL
- Features
-
- Compliant with MIPI CSI-2 Specification v1.0, v1.1, v1.3, v2.0,v2.1
- Compliant with D - PHY Specification v1.1,v1.2,v2.0,v2.1
- Compliant with C - PHY Specification v0.7,v1.2
- Full MIPI CSI-2 RX functionality where either D - PHY / C - PHY can be used
- Supports Multi lane distribution and also lanes can be configured up to 3 lanes for C - PHY and 8 lanes for D - PHY
- Supports Data rate in range 2.5 Gbps in DPHY Lanes.
- Supports Data rate in range of 0.8 Gsps to 6Gsps in CPHY Lanes.
- Supports PPI Interface.
- Supports short and long packets.
- Supports multilane distribution
- Continuous and non-continuous (gated) D-PHY byte clock support
- Supports Frame and Line Synchronization Packets (Short Packets)
- Supports Data Descrambling in Lanes
- Supports Deskew mechanism for Lane synchronization.
- Supports High Speed and Escape Mode (LPDT and ULPS) reception
- Supports the following interleaving methods
- Data type
- Virtual channel
- Supports 16 Virtual channel extension in D - PHY and 32 in C - PHY
- Support all Protocol Decoding Level errors
- Supports Error Detection techniques for active data using Checksum (16 bit)
- Supports Image applications with varying Pixel formats
- RAW Data Type - RAW6, RAW7, RAW8, RAW10, RAW12, RAW14, RAW16, RAW20
- RGB Data Type - RGB444, RGB555, RGB565, RGB888
- YUV Data Type - YUV422-8bit, YUV422-10bit, YUV420-8bit, YUV420-10bit, Legacy YUV20-8bit
- User defined data type - 8 bit
- Generic 8 bit long packet (Null, Blanking, Embedded data)
- Supports Pixel Level /interface to ISP with HSYNC , VSYNC , DATA and DATA VALID
- Programmable synchronization and interrupt (error and information) events
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- Benefits
-
- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- MIPI CSI-2 RX IP
-
SmartDV's MIPI CSI-2 RX IP contains following.
- The MIPI CSI-2 RX interface is available in Source and netlist products
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Integration testbench and tests
- Scripts for simulation and synthesis with support for common EDA tools
- Documentation contains User's Guide and Release notes
