MIPI DSI-2 RX interface provides full support for the two-wire MIPI DSI-2 RX synchronous serial interface, compatible with MIPI DSI and MIPI DSI 2 Specification version 3.1. Through its MIPI DSI-2 RX compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI DSI-2 RX IIP is proven in FPGA environment.The host interface of the MIPI DSI-2 RX can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Wishbone or Custom protocol.
MIPI DSI-2 RX IIP is supported natively in Verilog and VHDL
- Features
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- Compliant with MIPI DSI2 bus specification v1.0,v1.2,v3.1
- Full MIPI DSI2 Receiver functionality.
- Supports two types of PHY
- Supports data rate in range of 80 Mbps to 1500 Mbps in DPHY Lanes
- Supports data rate in range of 0.8Gsps to 6 Gsps in CPHY Lanes
- Supports PPI interface.
- Supports image applications with varying pixel formats
- Supports all types of short and long packets
- Supports 1to 4 lane configuration
- Supports all virtual channel identifier
- Supports both video and command modes
- Supports bi directional low power data transmission(LPDT)
- Supports Serial Display Interface (SDI), MIPI Display Pixel Interface (DPI SM), and Display Compression (DSC) input interface options
- Connects to MIPI D-PHY lane modules through PPI(up to 4 data lanes)
- Supports Programmable test video generator for integration debug and test
- 32 bit Arm AMBA 3 Advanced Peripheral Bus (APB) slave interface for register access
- Supports multiple packets per transmission
- Supports Deskew mechanism for lane Synchronization
- Supports 1-bit Error Correction and 2 bit Error Detection using ECC (6bit) for Packet header
- Supports Error Detection techniques for active data using Checksum(16 bit)
- Interrupt support for indicating internal status and error information
- Supports sync event payloads
- Supports display stream compression (DSC)
- Supports MIPI DSI-2 Specification.
- Supports MIPI DBI /DPIspecification
- Supports MIPI DCS specification
- Supports all BTA commands
- Supports Link Merging Function
- Supports both high speed and low power packet reception
- Supports error detection and correction techniques
- Supports following pixel formats
- YCbCr Data type
- 20 bit YCbCr 4:2:2
- 24 bit YCbCr 4:2:2
- 16 bit YCbCr 4:2:2
- 12 bit YCbCr 4:2:0
- RGB Data type
- 12 bit RGB 444 format
- 24 bit RGB 888 format
- 16 bit RGB 565 format
- 18 bit RGB 666 format
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- Benefits
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- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs,license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- MIPI DSI-2 RX IP
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SmartDV's MIPI DSI-2 RX IP contains following
- The MIPI DSI-2 RX interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Integration testbench and tests.
- Scripts for simulation and synthesis with support for common EDA tools.
- Documentation contains User's Guide and Release notes.
