MIPI_STP MASTER interface provides full support for the two-wire MIPI_STP MASTER synchronous serial interface, compatible with MIPI_STP specification. Through its MIPI_STP MASTER compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI_STP MASTER IIP is proven in FPGA environment.The host interface of the MIPI_STP MASTER can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Wishbone or Custom protocol.
MIPI_STP MASTER IIP is supported natively in Verilog and VHDL
- Features
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- Implemented in Unencrypted Verilog, VHDL and SystemC
- Compliant with MIPI STP Specification version 2.0 and 2.2.
- Supports STP interface.
- Supports ATB interface.
- Supports TPIU interface.
- Supports a trace stream comprised of 4-bit frames.
- Supports for merging trace data from up to 65536 independent data sources (Masters).
- Supports up to 65536 independent data Channels per Master.
- Supports basic trace data messages that can convey 4, 8, 16, 32, or 64 bit wide data.
- Supports Time-stamped data packets using one of several time stamp formats including:
- Gray code
- Natural binary
- Natural binary delta
- Export buffer depth (legacy STPv1 timestamp that requires DTC support).
- Supports Data packet markers to indicate packet usage by higher-level protocols.
- Supports Flag packets for marking points of interest (for higher-level protocols) in the stream.
- Supports Packets for aligning time stamps from different clock domains.
- Supports Packets for indicating to the DTC the position of a trigger event, which is typically used to control actions in the DTC.
- Supports Packets for cross-synchronization events across multiple STP sources.
- Supports for user-defined data packets.
- Facilities for synchronizing the trace stream on bit and message boundaries.
- Supports constraints Randomization.
- Status counters for various events in bus.
- Benefits
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- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- MIPI_STP MASTER IP
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SmartDV's MIPI_STP Master IP contains following.
- The MIPI_STP Master interface is available in Source and netlist products.
- The Source product is delivered in plain text verilog or VHDL or SystemC source code
- Integration testbench and tests
- Scripts for simulation and synthesis with support for common EDA tools
- Documentation contains User's Guide and Release notes.
