I2C/SMBus Verification IP provides an smart way to verify the I2C/SMBus bi-directional two-wire bus. The SmartDV's I2C/SMBus Verification IP is fully compliant with version 2.0 and version 3.0 of the SMBus Specifications and provides the following features.
I2C/SMBus VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
- Features
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- Supports SMBus specifications version 2.0 and version 3.0.
- Full I2C Master and Slave functionality.
- Supports all SMBus commands as per the specifications.
- Supports standard, fast, and high speed operations.
- Supports ARP sequence for SMBus mode.
- Support Timeout detection and generation.
- Alert generation and handling.
- Bus-accurate timing.
- Supports packet error checking for SMBus mode.
- Supports Master/Slave arbitration and clock synchronization.
- Glitch insertion and detection.
- Callbacks in Master, Slave and monitor for user processing of data.
- Supports scoreboard checking.
- Supports injection of errors and detection
- Master abort in middle of transaction
- Master doing ACK on last read access
- Master continue on NACK after write NACK from Slave
- Random and periodic clock period stretching by Slave
- Random write NACK insertion error by Slave
- Packet error check(PEC) error
- NACK for PEC code by Slave
- ACK for PEC code by Master
- Master asserted stop condition before PEC byte
- NACK for Command code byte by Slave
- NACK for second address byte after repeated start to same Slaves
- NACK for write size byte
- NACK for read size byte
- More than expected bytes were sent or received
- Less than expected bytes were sent or received
- Number of bytes field and actual bytes don't match
- NACK for read data from Master for bytes which is not last byte
- Master is driving SCL after sending NACK for read data
- Wrong ARP address
- Unsupported command codes
- Glitch insertion
- Timeout error insertion
- Status counters for various events in bus.
- Generates and handles glitches generating on both SMBDAT and SMBCLK lines.
- Supports timeouts forcing and handling.
- Built-in monitors for protocol checking, including a global bus monitor.
- Functional coverage to cover all functionality of SMBus Slave and Master.
- Support for multiple instantiations to create complex verification environment.
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
- SMBus Verification IP comes with complete testsuite to test every feature of SMBus specification.
- Benefits
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- Faster testbench development and more complete verification of I2C/SMBus designs.
- Easy to use command interface simplifies testbench control and configuration of Master and Slave.
- Simplifies results analysis.
- Runs in every major simulation environment.
- I2C/SMBus Verification Env
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SmartDV's I2C/SMBus Verification env contains following.
- Complete regression suite containing all the I2C/SMBus testcases.
- Examples showing how to connect various components, and usage of Master, Slave and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
