Ethernet 1G MAC core is compliant with IEEE Standard 802.3.2018 Ethernet specification. Through its Ethernet compatibility, it provides a simple interface to a wide range of low-cost devices. Ethernet 1G MAC IIP is proven in FPGA environment. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB,AHB-Lite,APB,AXI,AXI-Lite,Tilelink,OCP,VCI,Avalon,PLB,Wishbone or custom buses
ETHERNET 1G MAC IIP is supported natively in Verilog and VHDL
- Features
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- Compliant with IEEE Standard 802.3.2018 specification
- Supports Full duplex and Half duplex mode
- Supports GMII/MII Interfaces
- Supports MDIO (Clause 22 and Clause 45) Interface
- Supports Programmable Inter Packed Gap(IPG) and Preamble length
- Provides detailed statistics as per the specification
- Supports IEEE Standard 802.3az Energy Efficient Ethernet(EEE)
- Supports IEEE Standard 802.1Q and IEEE Standard 802.1ad VLAN
- Supports Wake-on-LAN
- Supports Loopback Functionality
- Supports Control frame and Jumbo frame
- Supports transmit and receive FIFO interface
- Supports FCS (CRC) transmission and reception
- Supports Pause frame based flow control in full duplex mode
- Supports AXI stream Interface for System Interface
- In house UNH compliance tested
- Optional support for TCP/IP offload
- Optional support for IEEE Standard 1588-2008 PTP
- Optional support for DMA on both transmit and receive side
- Optional supports RGMII,RMII and TBI interfaces
- Functional safety features (B: No certification, with safety features, in line with the development process
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to Microprocessor/Microcontroller devices
- Benefits
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- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's Ethernet 1G MAC IP contains following
- The Ethernet interface is available in Source and netlist products.
- The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
