Ethernet 10G KR PCS core is compliant with IEEE Standard 802.3.2018 Ethernet specification. Through its Ethernet compatibility, it provides a simple interface to a wide range of low-cost devices. Ethernet 10G KR PCS IIP is proven in FPGA environment. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB,AHB-Lite,APB,AXI,AXI-Lite,Tilelink,OCP,VCI,Avalon,PLB,Wishbone or custom buses
ETHERNET 10G KR PCS IIP is supported natively in Verilog and VHDL
- Features
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- Supports IEEE Standard 802.3.2018 Clause 49 for Base R PCS
- Supports 64b/66b encoding and decoding for transmit and receive path
- Supports data scrambling on the transmit path and descrambling on the receive path
- Supports gearbox for various XSBI data width
- Supports Block synchronization
- Supports Bit Error Rate monitoring
- Supports receiver Link fault status detection
- Supports Loopback functionality
- Supports IEEE 802.3az Energy Efficient Ethernet
- Supports Configurable Management Interface (MDIO(Clause 45) / SOC Bus)
- Supports XSBI Interface for the following data widths,
- 16 Bits
- 20 Bits
- 32 Bits
- 40 Bits
- 64 Bits
- Optional support for Forward error correction as per clause 74 of IEEE Standard 802.3.2018
- Optional support for Test pattern generation and error checkers
- Optionally supports auto negotiation for backplane Ethernet as per clause 73 of IEEE Standard 802.3.2018
- Optionally supports link training as per clause 72 of IEEE Standard 802.3.2018
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to Microprocessor/Microcontroller devices
- Benefits
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- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's Ethernet 10G KR PCS IP contains following
- The Ethernet interface is available in Source and netlist products.
- The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases.
- Lint, CDC, Synthesis, Simulation Scripts with waiver files.
- IP-XACT RDL generated address map.
- Firmware code and Linux driver package.
- Documentation contains User's Guide and Release notes.
