Ethernet 100G PCS core is compliant with IEEE Standard 802.3.2018 Ethernet specification. Through its Ethernet compatibility, it provides a simple interface to a wide range of low-cost devices. Ethernet 100G PCS IIP is proven in FPGA environment. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB,AHB-Lite,APB,AXI,AXI-Lite,Tilelink,OCP,VCI,Avalon,PLB,Wishbone or custom buses
ETHERNET 100G PCS IIP is supported natively in Verilog and VHDL
- Features
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- Supports IEEE Standard 802.3.2018 Clause 82
- Supports 100G BASE R, BASE KR4/CR4
- Supports 64b/66b encoding and decoding for transmit and receive path
- Supports data scrambling on the transmit path and descrambling on the receive path
- Supports Lane Distribution across 20 Lanes for 100Gbps BASE R and 4 lanes for BASE KR4/CR4
- Supports Block synchronization
- Supports gearbox for various data widths
- Supports Alignment Marker insertion and removal
- Supports PCS Lane Deskew and Lane Re-ordering
- Supports BIP-8 insertion on the transmit path and checking on the receive path per lane
- Supports Bit Error Rate monitoring
- Supports receiver Link fault status detection
- Supports Loopback functionality
- Supports IEEE 802.3az Energy Efficient Ethernet
- Supports Configurable Management Interface (MDIO(Clause 45) / SOC Bus)
- Supports PMA interface for the following widths,
- Support RS FEC as per clause 91 of IEEE Standard 802.3.2018
- Optional Support for Base-R FEC as per clause 74 of IEEE Standard 802.3.2018
- Optional support for Test pattern generation and error checkers
- Optional support for auto negotiation for backplane Ethernet as per clause 73 of IEEE Standard 802.3.2018
- Programmable PRBS31 and PRBS9 test pattern generation and checker
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to Microprocessor/Microcontroller devices
- Benefits
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- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's Ethernet 100G PCS IP contains following
- The Ethernet interface is available in Source and netlist products.
- The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases.
- Lint, CDC, Synthesis, Simulation Scripts with waiver files.
- IP-XACT RDL generated address map.
- Firmware code and Linux driver package.
- Documentation contains User's Guide and Release notes.
