SDI Verification IP implements the digital transmision systems as specified in Serial-Digital Interface standard for microprocessor-based sensors. SDI Verification IP provides an smart way to verify the SDI standard data transmission and control interfaces between recorder and sensor. The SmartDV's SDI Verification IP is fully compliant with SDI-12 Version 1.3 and provides the following features.
SDI VIP is supported natively in Verilog and VHDL
- Features
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- Supports SDI-12 Version 1.3
- Supports standard, fast, and high speed operations.
- Full SDI Recorder and Sensor functionality.
- Monitor, Detects and notifies the testbench of all protocol and timing errors.
- Supports all recorder commands & sensor responses specified in SDI-12 Version 1.3
- Supports all types of error insertion/detections as given below:
- Parity Errors
- CRC Errors
- Invalid response Errors
- Response timeout Errors
- Notifies the test bench of significant events such as transactions, warnings, and protocol violations.
- Status counters for various events.
- Callbacks in Recorder and Sensor for various events.
- Built in functional coverage analysis.
- SDI Verification IP comes with complete test suite to verify each and every feature of SDI-12 Version 1.3
- Benefits
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- Faster testbench development and more complete verification of SDI-12 designs.
- Easy to use command interface simplifies testbench control and configuration of Recorder,Sensor and monitor
- Simplifies results analysis.
- Runs in every major simulation environment.
- SDI Verification Env
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SmartDV's SDI Verification env contains following.
- Complete regression suite containing all the SDI testcases.
- Examples showing how to connect various components, and usage of Recorder,Sensor and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
