PMBus Verification IP provides an smart way to verify the PMBus component of a SOC or a ASIC. The SmartDV's PMBus Verification IP is fully compliant with standard PMBus 1.2 Specification and provides the following features.
PMBus VIP is supported natively in Verilog and VHDL
- Features
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- Fully compatible with PMBus 1.3.1 Specification
- Operates as a Master, Slave, or both.
- Support alert operation
- Bus-accurate timing
- PEC support
- Supports programmable clock frequency of operation
- Supports master/slave arbitration and clock synchronization
- Supports Fault Management and Reporting feature
- Supports re-synchronization of Slave
- Support Timeout detection and generation
- Support following commands
- Send byte command
- Receive byte command
- Write byte command
- Write word command
- Read byte command
- Read word command
- Process call command
- Block write command
- Block read command
- Group command
- Block write and read process call command
- Extended command read byte
- Extended command read word
- Extended command write byte
- Extended command write word
- Page Plus write command
- Page Plus read command
- Support AVS bus
- Supports following types of error injection and detection
- NACK for read data from master for bytes which is not last byte
- NACK for write data from slave for write data
- Master acked last read data
- Master is driving SCL after sending NACK for read data
- Master aborted in middle of byte transfer
- Packet error check error
- NACK for PEC code by slave
- ACK for PEC code by master
- Master asserted stop condition before PEC byte
- NACK for Command code byte by slave
- NACK for second address byte after repeated start to same slave
- NACK for write size byte
- NACK for read size byte
- More than expected bytes were send or received
- Less than expected bytes were send or received
- Number of bytes field and actual bytes don't match
- Random write NACK insertion error by slave
- Random and Periodic clock period stretching by slave
- Master continue on NACK after write NACK from salve
- Glitch insertion
- Timeout error insertion
- Implements all the registers and commands as per the PMBus specification
- Monitor, Detects and notifies the testbench of all protocol and timing errors.
- Compares read data with expected results
- Various kind of Master and Slave errors generation
- Glitch monitor and injection.
- Callbacks in master and slave for various events.
- Status counters for various events in bus.
- Benefits
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- Faster testbench development and more complete verification of PMBus designs.
- Easy to use command interface simplifies testbench control and configuration of master and slave
- Simplifies results analysis.
- Runs in every major simulation environment.
- PMBus Verification Env
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SmartDV's PMBus Verification env contains following.
- Complete regression suite containing all the PMBus testcases.
- Examples showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
