OCP Verification IP provides an smart way to verify the OCP component of a SOC or a ASIC. The SmartDV's OCP Verification IP is fully compliant with standard OCP Specification 3.1 and provides the following features.
OCP VIP is supported natively in Verilog and VHDL
- Features
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- Compliant with OCP 3.1 specification.
- Supports OCP Master, OCP Slave, OCP MOnitor and OCP Checker.
- Supports all OCP protocol transfer & command types.
- Supports all OCP protocol signal widths including address and data.
- Supports all OCP protocol burst models, burst lengths and response types.
- SRMD and MRMD bursts support.
- Ability to pipeline transfers and non-blocking flow control support.
- Supports concurrency and out-of-order processing of transfers: Multi-threading and tagging support.
- Request interleaving support.
- Master/Slave Connect-Disconnect feature support.
- Supports 2-Dimensional block burst address sequences.
- Compliance to phase-ordering rules.
- Complete support for full range of OCP configurations.
- Asynchronous/synchronous reset and EnableClk mechanism. On the fly reset control.
- Support for ThreadBusy behavior.
- Supports all sideband signals.
- Coherence Extensions support.
- Consistency checks for configuration parameters.
- Slave supports fine grain control of response per address or per transfer.
- Supports constrained randomization of protocol attributes.
- Programmable Timeout insertion.
- Supports FIFO memory.
- Rich set of configuration parameters to control OCP functionality.
- On-the-fly protocol and data checking.
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
- Built in coverage analysis.
- Callbacks in master, slave and monitor for various events.
- Status counters for various events on bus.
- OCP Verification IP comes with complete testsuite to test every feature of OCP 3.1 specification.
- Benefits
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- Faster testbench development and more complete verification of OCP designs.
- Easy to use command interface simplifies testbench control and configuration of master and slave.
- Simplifies results analysis.
- Integrates easily into OpenVera, SytemVerilog, Specman E, and SystemC
- Runs in every major simulation environment.
- OCP Verification Env
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SmartDV's OCP Verification env contains following.
- Complete regression suite containing all the OCP testcases.
- Examples showing how to connect various components and usage of BFM and Monitor.
- Detailed documentation of all classes, tasks and functions used in verification env.
- Documentation also contains User's Guide and Release notes.
