• Home
  • About Us
    • Partners
    • Careers
  • Products
    • Verification IP's
      • MIPI Verification IP's
      • Networking and SOC Verification IP's
      • Automotive And Serial Bus Verification IP's
      • Storage And Video Verification IP's
    • Memory Model's
      • DDR SDRAM Memory Models
      • Low Power Memory Models
      • Graphics Memory Models
      • Flash Memory Models
      • High Bandwidth Memory Models
      • SDRAM Memory Models
      • SRAM Memory Models
      • Non volatile Memory Models
      • DIMM Memory Models
      • Misc Memory Models
      • DFI Verification IP's
    • SimXL - Emulation Models
      • MIPI Synthesizable Transactors
      • Networking and SOC Synthesizable Transactors
      • Automotive And Serial Bus Synthesizable Transactors
      • Storage And Video Synthesizable Transactors
      • DDR SDRAM Memory Synthesizable Transactors
      • Low Power Memory Synthesizable Transactors
      • Graphics Memory Synthesizable Transactors
      • Flash Memory Synthesizable Transactors
      • High Bandwidth Memory Synthesizable Transactors
      • SDRAM Memory Synthesizable Transactors
      • SRAM Memory Synthesizable Transactors
      • DIMM Memory Synthesizable Transactors
      • Misc Memory Synthesizable Transactors
    • Formal Verification IP (Assertion IP)
      • Networking and SOC Assertion IP's
      • DDR SDRAM Memory Assertion IP's
      • Low Power Memory Assertion IP's
      • Graphics Memory Assertion IP's
      • SDRAM Memory Assertion IP's
      • Misc Memory Assertion IP's
      • Serial Assertion IP's
    • Post Silicon Validation IP's
      • MIPI Post Silicon Validation IP's
    • Design IP's
      • MIPI Design IP's
      • Networking and SOC Design IP's
      • DMA Controller Design IP's
      • Automotive Design IP's
      • Serial Bus Design IP's
      • Audio Video Design IP's
      • Memory Controller Design IP's
  • Customers
  • News & Events
  • Support
  • Contact Us
Products

MIPI DBI VIP

MIPI DBI VIP

MIPI DBI Verification IP provides an smart way to verify the MIPI DBI bus. The SmartDV's MIPI DBI Verification IP is fully compliant with version 2.0 MIPI Alliance specification and provides the following features.

MIPI DBI VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

MIPI DBI VIP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Features
  • Compliant to MIPI DBI v2.0 Specification.
  • Supports Type A, Type B and Type C Interfaces.
  • Supports Type 1, Type 2 and Type 3 Architecture.
  • Supports all types of Display Command Set types
  • Supports Data width of 8, 9 or 16 bits
  • Ablity control timing fine grain
  • Supports all color formats mentioned in specification
  • Supports reading pixel data from text files
  • Error Injection
    • Reserved bit Error
    • Write less number of parameter error
    • Write more number of parameter error
    • Read less number of parameter error
    • Read more number of parameter error
    • Color data error
  • FIFO depth is programmable
  • Callback in BFM and Monitor for wide range of events to help execute user code.
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Status counters for various events in bus.
  • MIPI DBI Verification IP comes with complete testsuite to test every feature of MIPI DBI specification.
  • Functional coverage for complete MIPI DBI features.
Benefits
  • Faster testbench development and more complete verification of MIPI DBI designs.
  • Easy to use command interface simplifies testbench control and configuration of Host, Display and Monitor
  • Simplifies results analysis.
  • Runs in every major simulation environment.
MIPI DBI Verification Env

    Note: Only mails from offical mail ID will be processed

    Request Datasheet
    Request Evaluation

    SmartDV's MIPI DBI Verification env contains following.

  • Complete regression suite containing all the MIPI DBI testcases.
  • Examples showing how to connect various components, and usage of Host, Display and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Give us your feedback

Was this page helpful?
Ask us a question or get help

Talk to Us

Partner with us

Develop Custom VIP's
Partner for design IP's

Send Enquiry

Quick Contact

A value is required.
A value is required.
A value is required.
A value is required.
Copyright © 2020 SmartDV Technologies India Private Limited All rights reserved.