Local Interconnect Network (LIN) is a single-wire, serial communication protocol based on the UART interface that is gaining popularity as a sub-bus standard in the automotive industry. LIN VIP are reusable components that provide ready made verification environment. Compatible with Local Interconnect Network (LIN) specifications version 2.2A and supports all the frame types such as Unconditional, Event-triggered, Sporadic, Diagnostic and Reserved frames.
LIN 2.2A VIP includes an extensive test suite covering most of the possible scenarios. It can perform all protocal tests and moreover it allows an easy generation of very high number of patterns and a set of specified patterns to stress the DUT.
LIN VIP is supported natively in Verilog and VHDL
- Features
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- Compatible with Local Interconnect Network (LIN) specifications version 2.2A
- Support Master and multiple Slaves.
- Compliant with ISO/DIS 17987-2, ISO/DIS 17987-3 and ISO/DIS 17987-4.
- Supports test cases as per standard
- INTERNATIONAL STANDARD ISO/DIS 17987-6.
- Supports all frame types.
- Unconditional frames
- Event-triggered frames
- Sporadic frames
- Diagnostics frames
- Reserved frames
- Supports programmable clock frequency of operation.
- Simulates LIN cluster with number of nodes the user requires.
- These LIN nodes can be configured as Master or Slave nodes.
- The DUT can either be a LIN 2.2A master or slave device.
- Supports cluster wake up and go to sleep.
- Supports number of stop bit configuration.
- Supports all types of error insertion and detection
- Checksum error
- Checksum start/stop error
- Parity error
- Sync pattern error
- Sync start/stop error
- PID start/stop error
- Data start/stop error
- Break length error
- Break delimiter error
- Diagnostic frame errors
- Glitch insertion and detection
- Monitors, detects and notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
- Allows creation of both random and directed testcases as well as constraints randomization.
- Status counters for various events on bus.
- Supports callbacks in monitor, slave and master BFMs for user processing of data.
- LIN Verification IP comes with complete testsuite to test every feature of LIN specification.
- Functional coverage for complete LIN 2.2A features.
- Benefits
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- Faster testbench development and more complete verification of LIN designs.
- Easy to use command interface simplifies testbench control and configuration of slave and master.
- Simplifies results analysis.
- Runs in every major simulation environment.
- LIN Verification Env
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SmartDV's LIN Verification env contains following.
- Complete regression suite containing all the LIN testcases.
- Examples showing how to connect various components, and usage of Master, Slave and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
