I2C Verification IP provides an smart way to verify the I2C bi-directional two-wire bus. The SmartDV's I2C Verification IP is fully compliant with version 2.1, 3.0 and 6.0 of the Philip's I2C-Bus Specification and provides the following features.
I2C VIP is supported natively in Verilog and VHDL
- Features
-
- Supports 6.0 I2C Specification.
- Full I2C Master and Slave functionality.
- Supports all I2C clocking speeds including HS mode, Fast mode, Fast mode plus
- and Ultra-fast mode.
- Operates as a Master, Slave, or both.
- Start, repeat start and stop for all possible transfers.
- 7b/10b configurable slave address.
- Allows testing of various bus traffic for Read, Write, General Call and CBUS.
- Supports complex sequence of 7/10 bit with repeated start command sequences.
- Supports Bus-accurate timing.
- Supports START byte generation and handling.
- Supports master/slave arbitration and clock synchronization.
- Supports Glitch insertion and detection.
- Supports insertion of wait states by slave and master.
- Supports AT24C1024 EEPROM memory model which supports 256 bytes Page Write Mode.
- Supports Random and Sequential Read Modes.
- Supports injection of various errors
- Master aborting in middle of transaction
- Master doing ACK on last read access
- Master continue after NACK from slave for write data
- Random and Periodic clock period stretching by slave
- Random Write NACK insertion by slave
- Glitch insertion on clock and data at various windows
- Monitor, detects and notifies the testbench of all protocol and timing errors.
- Callbacks in master and slave for various events.
- Status counters for various events in bus.
- Functional coverage to cover all functionality of I2C slave and master
- I2C Verification IP comes with complete testsuite to test every feature of I2C
- specification.
- Benefits
-
- Faster testbench development and more complete verification of I2C designs.
- Easy to use command interface simplifies testbench control and configuration of TX and RX.
- Simplifies results analysis.
- Runs in every major simulation environment.
- I2C Verification Env
-
SmartDV's I2C Verification env contains following.
- Complete regression suite containing all the I2C testcases to certify I2C slave/master device
- Examples showing how to connect various components, and usage of Master, Slave and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
