GMII TBI (8b/10b) Ethernet VIP

The Gigabit Ethernet Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY layer interfaces of designs with a 1G Ethernet interface GMII TBI. It can work with SystemVerilog,Vera, SystemC, E and Verilog HDL environment. GMII TBI verification IP is developed by experts in Ethernet, who have developed ethernet products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a ethenet product.

GMII TBI (8b/10b) Ethernet VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env



  • Follows GMII/TBI specification as defined in IEEE 802.3.
  • Supports injection of following errors
    • Oversize, undersize, inrange, out of range Packet size errors
    • Missing SPD/EPD/SFD framing errors
    • CRC Error
    • Wrong /T/R/ insertion
    • Disparity error injection
    • Invalid /D/ and /K/ character injection
    • Variable preamble and IPG insertion
  • Supports auto-negotation as per SGMII
  • Supports auto-negotation as per Clause-37 of 802.3
  • Comes with GMII TBI Tx BFM, GMII TBI Rx BFM, and GMII TBI Monitor
  • Monitor supports detection of all protocol violations.
  • Supports Pause frame generation and detection.
  • Built in coverage analysis.


  • Faster testbench development and more complete verification of GMII TBI designs.
  • Easy to use command interface simplifies testbench control and configuration of GMII TBI TX and RX.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

GMII TBI Verification Env

SmartDV's GMII TBI Verification env contains following.

  • Complete regression suite (UNH) containing all the GMII TBI testcases.
  • Examples showing how to connect various components, and usage of TXRX BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

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