• Home
  • About Us
    • Partners
    • Careers
  • Products
    • Verification IP's
      • MIPI Verification IP's
      • Networking and SOC Verification IP's
      • Automotive And Serial Bus Verification IP's
      • Storage And Video Verification IP's
    • Memory Model's
      • DDR SDRAM Memory Models
      • Low Power Memory Models
      • Graphics Memory Models
      • Flash Memory Models
      • High Bandwidth Memory Models
      • SDRAM Memory Models
      • SRAM Memory Models
      • Non volatile Memory Models
      • DIMM Memory Models
      • Misc Memory Models
      • DFI Verification IP's
    • SimXL - Emulation Models
      • MIPI Synthesizable Transactors
      • Networking and SOC Synthesizable Transactors
      • Automotive And Serial Bus Synthesizable Transactors
      • Storage And Video Synthesizable Transactors
      • DDR SDRAM Memory Synthesizable Transactors
      • Low Power Memory Synthesizable Transactors
      • Graphics Memory Synthesizable Transactors
      • Flash Memory Synthesizable Transactors
      • High Bandwidth Memory Synthesizable Transactors
      • SDRAM Memory Synthesizable Transactors
      • SRAM Memory Synthesizable Transactors
      • DIMM Memory Synthesizable Transactors
      • Misc Memory Synthesizable Transactors
    • Formal Verification IP (Assertion IP)
      • Networking and SOC Assertion IP's
      • DDR SDRAM Memory Assertion IP's
      • Low Power Memory Assertion IP's
      • Graphics Memory Assertion IP's
      • SDRAM Memory Assertion IP's
      • Misc Memory Assertion IP's
      • Serial Assertion IP's
    • Post Silicon Validation IP's
      • MIPI Post Silicon Validation IP's
    • Design IP's
      • MIPI Design IP's
      • Networking and SOC Design IP's
      • Automotive Design IP's
      • Serial Bus Design IP's
      • Audio Video Memory Design IP's
  • Customers
  • News & Events
  • Support
  • Contact Us
Products

ARINC 825 VIP

ARINC 825 VIP

ARINC 825 Verification IP implements the digital transmision system have been specified for inter-unit and inter-systems communications on board transport aircraft. ARINC 825 Verification IP provides an smart way to verify the ARINC 825 standard data transmission and control interfaces between transmitter and receiver.The SmartDV's ARINC 825 Verification IP is fully compliant with ARINC specification 825 - 2 and provides the following features.

ARINC 825 VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

ARINC 825 VIP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Features
  • Supports ARINC specification 825 - 2.
  • Supports one of the following data rates
    • 83.33 Kbit/s
    • 125 Kbit/s
    • 250 Kbit/s
    • 500 Kbit/s
    • 1 Mbit/s
  • The model has a rich set of configuration parameters to control ARINC 825 functionality.
  • Supports one-to-many communication and also peer-to-peer communication.
  • Supports all the four frame types.
    • Data frames
    • Remote frames
    • Error frames
    • Overload frames
  • Remote frame support.
    • Automatic transmission after reception of remote transmission request (RTR).
    • Automatic receive after transmission of an RTR.
  • Supports all the five types of error insertion and detection.
    • Bit errors
    • Stuff errors
    • CRC errors
    • Format errors
    • Acknowledgement errors
  • Supports all the node service interface as per ARINC 825 -2 specification.
    • Node service concept[NSC]
    • Node identification service[IDS]
    • Node synchronization service[NSS]
    • Data upload service[DUS]
    • Data download service[DDS]
    • Bit control service[BCS]
    • Non-volatile storage service[NVS]
    • Node-ID setting service[NIS]
    • Service control service[SCS]
  • Tracks TEC/REC error counter and fault states.
  • Support Broadcast and acknowledgement by all nodes.
  • Supports Bit by bit Arbitrations.
  • Glitch insertion and detection
  • Re-transmission of corrupted messages.
  • Status counters for various events on bus.
  • Monitors, detects and notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Supports constraints Randomization.
  • Callbacks in transmitter,receiver and monitor for various events.
  • Built in functional coverage analysis.
Benefits
  • Faster testbench development and more complete verification of ARINC 825 designs.
  • Easy to use command interface simplifies testbench control and configuration of Transmitter,Receiver and Monitor
  • Simplifies results analysis.
  • Runs in every major simulation environment.
ARINC 825 Verification Env

    Note: Only mails from offical mail ID will be processed

    Request Datasheet
    Request Evaluation

    SmartDV's ARINC 825 Verification env contains following.

  • Complete regression suite containing all the ARINC 825 testcases.
  • Examples showing how to connect various components, and usage of Transmitter,Receiver and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Give us your feedback

Was this page helpful?
Ask us a question or get help

Talk to Us

Partner with us

Develop Custom VIP's
Partner for design IP's

Send Enquiry

Quick Contact

A value is required.
A value is required.
A value is required.span>
A value is required.
Copyright © 2019 SmartDV Technologies India Private Limited All rights reserved.