SMBus Synthesizable Transactor provides a smart way to verify the SMBus component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's SMBus Synthesizable Transactor is fully compliant with version of 3.0 SMBus Specification and provides the following features.
- Features
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- Supports SMBus specification version 3.0
- Supports all SMBus device types: Master, Slave
- Supports all SMBus command as per the specs
- Supports programmable clock frequency of operation
- Supports ARP command generation and response
- Supports Timeout detection and generation
- Alert generation and handling
- Supports bus-accurate timing
- Supports packet error checking
- Supports master/slave arbitration and clock synchronization
- Supports glitch insertion and detection
- Supports insertion of errors
- Master aborting in middle of transaction
- ACK on last read phase by master
- Master doing ACK on last read access
- Master continue on NACK after write NACK from slave
- Random and Periodic clock period stretching by slave
- Random Write NACK insertion by slave
- Glitch injection on clock and data at various windows
- PEC error
- Timeout error insertion
- ACK for PEC field by master for read data
- Wrong ARP address
- Unsupported command codes
- Illegal commands lengths
- Generates and handles glitches generating on both SMBDAT and SMBCLK lines
- Supports timeouts forcing and handling
- Support for multiple instantiations to create complex verification environment
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations
- SMBus Verification IP comes with complete testsuite to test every feature of SMBus specification
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- SMBus Synthesizable Env
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SmartDV's SMBus Synthesizable env contains following:
- Synthesizable transactors
- Complete regression suite containing all the SMBus testcases
- Examples showing how to connect and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation also contains User's Guide and Release notes
