OBSAI Synthesizable VIP provides an smart way to verify the OBSAI component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's OBSAI Synthesizable VIP is fully compliant with standard OBSAI Specification and provides the following features.
- Features
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- Compliant with OBSAI Reference Point 1 Specification Version 2.1 and Reference Point 3 Specification Version 4.2
- Supports complete OBSAI Tx/Rx functionality
- Supports the Physical link layer of the OBSAI RP3 specification
- Supports the Data link layer of the OBSAI RP3 specification
- Supports test cases as per standard
- Conformance Test Specification Version 1.01
- Supports the different standard bit rates of the OBSAI specification
- 768 Mbps
- 1536 Mbps
- 3072 Mbps
- 6144 Mbps
- Supports CDMA/WCDMA/802.16/LTE framing formats
- Supports Frame Clock Burst Messages
- Supports RTT Measurement
- Supports Virtual Hardware Reset
- Supports Line Rate Auto-Negotiation
- Supports Ethernet Messaging
- Supports Transport layer multiplexing/demultiplexing
- Supports scrambler as in OBSAI specification
- Supports scrambler enabling and disabling
- Supports insertion of scrambler errors
- Supports disparity and invalid code insertion in 8b/10b
- Detects and reports the following errors
- Invalid control character
- Invalid data character
- Invalid 10bit code
- Scrambler errors
- Disparity errors
- Under and oversize frame
- CRC errors
- Framing errors
- Supports glitch insertion and detection
- Supports bus accurate timing and timing checks
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- OBSAI Synthesizable Env
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SmartDV's OBSAI Synthesizable env contains following:
- Synthesizable transactors
- Examples showing how to connect and usage of Synthesizable VIP
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation also contains User's Guide and Release notes
