• Home
  • About Us
    • Partners
    • Careers
  • Products
    • Verification IP's
      • MIPI Verification IP's
      • Networking and SOC Verification IP's
      • Automotive And Serial Bus Verification IP's
      • Storage And Video Verification IP's
    • Memory Model's
      • DDR SDRAM Memory Models
      • Low Power Memory Models
      • Graphics Memory Models
      • Flash Memory Models
      • High Bandwidth Memory Models
      • SDRAM Memory Models
      • SRAM Memory Models
      • Non volatile Memory Models
      • DIMM Memory Models
      • Misc Memory Models
      • DFI Verification IP's
    • SimXL - Emulation Models
      • MIPI Synthesizable Transactors
      • Networking and SOC Synthesizable Transactors
      • Automotive And Serial Bus Synthesizable Transactors
      • Storage And Video Synthesizable Transactors
      • DDR SDRAM Memory Synthesizable Transactors
      • Low Power Memory Synthesizable Transactors
      • Graphics Memory Synthesizable Transactors
      • Flash Memory Synthesizable Transactors
      • High Bandwidth Memory Synthesizable Transactors
      • SDRAM Memory Synthesizable Transactors
      • SRAM Memory Synthesizable Transactors
      • DIMM Memory Synthesizable Transactors
      • Misc Memory Synthesizable Transactors
    • Formal Verification IP (Assertion IP)
      • Networking and SOC Assertion IP's
      • DDR SDRAM Memory Assertion IP's
      • Low Power Memory Assertion IP's
      • Graphics Memory Assertion IP's
      • SDRAM Memory Assertion IP's
      • Misc Memory Assertion IP's
      • Serial Assertion IP's
    • Post Silicon Validation IP's
      • MIPI Post Silicon Validation IP's
    • Design IP's
      • MIPI Design IP's
      • Networking and SOC Design IP's
      • DMA Controller Design IP's
      • Automotive Design IP's
      • Serial Bus Design IP's
      • Audio Video Design IP's
      • Memory Controller Design IP's
  • Customers
  • News & Events
  • Support
  • Contact Us
Products

MIPI STP Synthesizable VIP

MIPI STP Synthesizable VIP

MIPI STP Synthesizable Verificaction IP provides a smart way to verify the MIPI STP component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's MIPI STP Synthesizable VIP is fully compliant with standard MIPI STP Specification and provides the following features.

Features
  • Compliant with MIPI STP Specification version 2.0 and 2.2
  • Supports STP interface
  • Supports ATB interface
  • Supports TPIU interface
  • Supports a trace stream comprised of 4-bit frames
  • Supports for merging trace data from up to 65536 independent data sources (Masters)
  • Supports up to 65536 independent data Channels per Master
  • Supports basic trace data messages that can convey 4, 8, 16, 32, or 64 bit wide data
  • Supports Time-stamped data packets using one of several time stamp formats including
    • Gray code
    • Natural binary
    • Natural binary delta
    • Export buffer depth (legacy STPv1 timestamp that requires DTC support)
  • Supports Data packet markers to indicate packet usage by higher-level protocols
  • Supports Flag packets for marking points of interest (for higher-level protocols) in the stream
  • Supports Packets for aligning time stamps from different clock domains
  • Supports Packets for indicating to the DTC the position of a trigger event, which is typically used to control actions in the DTC
  • Supports Packets for cross-synchronization events across multiple STP sources
  • Supports for user-defined data packets
  • Facilities for synchronizing the trace stream on bit and message boundaries
  • Supports all types of error insertion and detection
    • Invalid Time-stamp format
    • Invalid opcode
    • Invalid async pattern
    • Invalid version
Benefits
  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms
MIPI STP Synthesizable Env

    Note: Only mails from offical mail ID will be processed

    Request Datasheet
    Request Evaluation

    SmartDV's MIPI STP Synthesizable env contains following:

  • Synthesizable transactors
  • Complete regression suite containing all the MIPI STP testcases
  • Examples showing how to connect and usage of Synthesizable VIP
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation also contains User's Guide and Release notes

Give us your feedback

Was this page helpful?
Ask us a question or get help

Talk to Us

Partner with us

Develop Custom VIP's
Partner for design IP's

Send Enquiry

Quick Contact

A value is required.
A value is required.
A value is required.
A value is required.
Copyright © 2020 SmartDV Technologies India Private Limited All rights reserved.