LPDDR3 Synthesizable Memory Model provides a smart way to verify the LPDDR3 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's LPDDR3 Synthesizable memory model is fully compliant with standard LPDDR3 Specification and provides the following features.
- Features
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- Supports LPDDR3 memory devices from all leading vendors.
- Supports 100% of LPDDR3 protocol standard JESD209-3, JESD209-3B and JESD209-3C.
- Supports all the LPDDR3 commands as per the specs.
- Supports up to 32GB device density
- Supports the following devices.
- Supports all data rates as per specification.
- Supports Programmable READ/WRITE Latency timings.
- Supports Burst sequence.
- Checks for following
- Check-points include power up, initialization and power off rules,
- State based rules, Active Command rules,
- Read/Write Command rules etc.
- All timing violations.
- Supports All Mode register programming.
- Supports write data mask and data strobe features.
- Supports Power Down features.
- Supports Deep Power Down features.
- Supports Write leveling.
- Supports ZQ calibration.
- Supports CA training and DQ calibration.
- Supports ODT (On-Die Termination features).
- Supports full-timing as well as behavioral versions in one model.
- On-the-fly protocol and data checking
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- LPDDR3 Synthesizable VIP Env
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SmartDV's LPDDR3 Verification VIP env contains following:
- Synthesiable transactors
- Complete regression suite containing all the LPDDR3 testcases
- Example's showing how to connect various components, and usage of Synthesiable Memory model
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation also contains User's Guide and Release notes
