LPDDR3 Synthesizable Memory Model provides an smart way to verify the LPDDR3 component of a SOC or a ASIC. The SmartDV's LPDDR3 Synthesizable memory model is fully compliant with standard LPDDR3 Specification and provides the following features. Better than Denali Memory Models.
LPDDR3 Synthesizable Memory Model is supported natively in Verilog and VHDL
- Features
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- Supports LPDDR3 memory devices from all leading vendors.
- Supports 100% of LPDDR3 protocol standard JESD209-3 and JESD209-3B.
- Supports all the LPDDR3 commands as per the specs.
- Quickly validates the implementation of the LPDDR3 standard JESD209-3 and JESD209-3B.
- Constantly monitors LPDDR3 behavior during simulation.
- On-the-fly protocol and data checking.
- Support burst length of 8.
- Supports ODT(On-Die Termination features).
- Supports Programmable READ/WRITE Latency timings.
- Checks for following
- Check-points include power up,initialization and power off rules,
- State based rules, Active Command rules,
- Read/Write Command rules etc.
- All timing violations.
- Support for All Mode registers programming.
- Support CA training and DQ calibration.
- Support write data mask and data strobe features.
- Support for Power Down features.
- Support for input clock stop and frequency change.
- Support for full-timing as well as behavioral versions in one model.
- Support for all timing delay ranges in one model: min, typical and max.
- Protocol Checker fully compliant with LPDDR3 Specification JESD209-3 and JESD209-3B compliants.
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
- Built in functional coverage analysis.
- Supports Callbacks, so that user can access the data observed by monitor.
- Benefits
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- Compatible with testbench writting using SmartDV VIP's
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment.
- Runs in custom FPGA platforms
- LPDDR3 Verification Env
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SmartDV's LPDDR3 Verification env contains following.
- Complete regression suite containing all the LPDDR3 testcases.
- Complete UVM/OVM sequence library for LPDDR3 controller.
- Examples's showing how to connect and usage of Model.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
