I2C/SMBus Synthesizable VIP provides an smart way to verify the I2C/SMBus bi-directional two-wire bus. The SmartDV's I2C/SMBus Synthesizable VIP is fully compliant with version 2.1 of the Philip's I2C-Bus Specification and SMBus 2.0 Specification and provides the following features.
I2C/SMBus Synthesizable VIP is supported natively in Verilog and VHDL
- Features
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- Supports standard, fast, and high speed operations.
- Full I2C Master and Slave functionality.
- Supports packet error checking for SMBus mode
- Supports ARP sequence for SMBus mode
- Operates as a Master, Slave, or both.
- Monitor, Detects and notifies the testbench of all protocol and timing errors.
- Supports all I2C clocking speeds
- 7b/10b configurable slave address
- Compares read data with expected results
- Bus-accurate timing
- Various kind of Master and Slave errors generation
- Glitch monitor and injection.
- Supports timeouts forcing and handling in SMBus mode
- Callbacks in master and slave for various events.
- Status counters for various events in bus.
- Benefits
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- Compatible with testbench writting using SmartDV VIP's
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment.
- Runs in custom FPGA platforms
- I2C/SMBus Synthesizable VIP Env
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SmartDV's I2C/SMBus Synthesizable env contains following.
- Synthesizable transactors
- Complete regression suite containing all the UART testcases.
- Examples showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation contains User's Guide and Release notes.
