GDDR5 Synthesizable Memory Model provides a smart way to verify the GDDR5 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's GDDR5 Synthesizable memory model is fully compliant with standard JESD212C Specification and provides the following features.
- Features
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- Supports 100% of GDDR5 protocol standard JESD212C
- Supports all the GDDR5 commands as per the specs
- Supports all types of timing and protocol violation detection
- Supports up to 8GB device density
- Supports following device modes:
- Supports all mode registers programming
- Checks for following:
- Check-points include power on, initialization and power off rules
- State based rules, active command rules
- Read/write command rules etc
- All timing violations
- Supports single ended interface for command, address and data
- Supports double data rate (DDR) data (WCK)
- Supports single data rate (SDR) command (CK)
- Supports double data rate (DDR) addressing (CK)
- Supports programmable burst length: 8
- Supports programmable read latency and write latency
- Supports write data mask function via address bus
- Supports data bus inversion (DBI) & address bus inversion (ABI)
- Supports input/output PLL/DLL
- Supports address training
- Supports cyclic redundancy check (CRC-8)
- Supports programmable CRC read latency, write latency
- Supports low power modes
- Supports auto & self refresh modes
- Supports auto precharge option for each burst access
- Supports on-die termination (ODT) for all high-speed inputs
- Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- GDDR5 Synthesizable VIP Env
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SmartDV's GDDR5 Synthesizable VIP env contains following:
- Synthesizable transactors
- Complete regression suite containing all the GDDR5 testcases
- Examples showing how to connect various components, and usage of Synthesizable Memory model
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes
