eMMC Synthesizable VIP is an advanced solution in the market for the verification of eMMC implementations. It is adherent with eMMC standard JESD84-A441, JESD84-B45,JESD84-B50 & JESD84-B51. It can generate all command types. The eMMC VIP monitor acts as powerful protocol-checker, fully compliant with eMMC JESD84-B51 specification.
eMMC JESD84-A441, JESD84-B45,JESD84-B50 & JESD84-B51 includes extensive test suite covering most of the possible scenarios and eMMC conformance norms. eMMC JESD84-A441, JESD84-B45,JESD84-B50 & JESD84-B51 VIP can perform all protocol tests as testbench and moreover it allows an easy generation of a very high number of patterns and a set of specified patterns to stress the DUT.eMMC Synthesizable VIP provides an smart way to verify the UART component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's eMMC Synthesizable VIP is fully compliant with standard UART 16550 Specification and provides the following features.
eMMC Synthesizable VIP is supported natively in Verilog and VHDL
- Features
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- Compliant with eMMC JESD84-A441, JESD84-B45, JESD84-B50, JESD84-B51 specification.
- Single byte, single block, multiple block (finite and infinite) transfers.
- Supports stream transfer operations.
- Supports three different data width bus modes
- 1-bit(default)
- 4-bit
- 8-bit
- Supports boot opeartion mode with simple boot sequence method.
- Supports alternative boot operation mode
- Supports password protection of data
- Supports higher than 2GB of density of memories.
- Supports send tuning block(CMD21) command
- Supports HS200 mode and HS400 mode
- Supports high speed boot.
- Supports command queuing
- Supports Enhanced Strobe
- Supports Extended Security Protocols Commands
- Supports Production State Awareness
- Supports Secure Write Protect Mode
- Supports Replay Protected Memory Block(RPMB) functionality
- Supports packed commands
- Supports data removable mechanisms
- Supports high voltage & dual voltage
- Supports hardware reset signal
- Supports single data rate & dual data rate
- Supports write protection features for the boot and user areas, which may be permanent, power-on or temporary
- Tracking of the transmit and receive counters.
- Protocol Checker fully compliant with eMMC JESD84-A441, JESD84-B45 ,JESD84-B50 and JESD84-B51 Specification.
- Functional coverage for complete JESD84-A441, JESD84-B45,JESD84-B50 and JESD84-B51.
- Complete testsuite.
- Detects and reports the following errors.
- Out of range error
- Address misalign error
- CRC error
- Switch error
- Illegal command error
- Block length error
- Lock-unlock failed error
- Erase sequence error
- Direction bit error
- Stuff bit error
- Erase param error
- Parameter error
- Invalid voltage error
- Reserved bit error
- WP violation error
- CSD/CID over write error
- Supports constraints Randomization.
- Configurable as agent (frame generator) or monitor.
- Bus-accurate timing.
- Monitor, Detects and notifies the testbench of all protocol errors.
- Benefits
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- Compatible with testbench writting using SmartDV VIP's
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment.
- Runs in custom FPGA platforms
- eMMC Synthesizable VIP Env
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SmartDV's eMMC Synthesizable env contains following.
- Synthesizable transactors
- Complete regression suite containing all the UART testcases.
- Examples showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation contains User's Guide and Release notes.
