DDR Synthesizable Memory Model provides a smart way to verify the DDR component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's DDR Synthesizable memory model is fully compliant with standard JESD79F Specification and provides the following features.
- Features
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- Supports 100% of DDR protocol standard JESD79F
- Supports all the DDR commands as per the specs
- Supports all device speeds as per specification
- Supports Programmable CAS latency
- Supports Programmable burst lengths: 2,4 and 8
- Supports Write data Mask
- Supports the following devices
- Supports up to 1 GB device density
- Supports the following burst types
- Supports burst order
- Supports All Mode register programming
- Supports Extended Mode register programming
- Supports Auto refresh & self-refresh modes
- Supports Auto precharge option for each burst access
- Supports Power Down features
- Supports DLL operation
- Checks for following
- Check-points include power up, initialization and power off rules
- State based rules, Active Command rules
- Read/Write Command rules etc
- All timing violations
- Bus-accurate timing for min, max and typical values.
- Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- DDR Synthesizable VIP Env
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SmartDV's DDR Synthesizable VIP env contains following:
- Synthesizable transactors
- Complete regression suite containing all the DDR testcases
- Examples showing how to connect various components, and usage of Synthesizable Memory model
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes
