• Home
  • About Us
    • Partners
    • Careers
  • Products
    • Verification IP's
      • MIPI Verification IP's
      • Networking and SOC Verification IP's
      • Automotive And Serial Bus Verification IP's
      • Storage And Video Verification IP's
    • Memory Model's
      • DDR SDRAM Memory Models
      • Low Power Memory Models
      • Graphics Memory Models
      • Flash Memory Models
      • High Bandwidth Memory Models
      • SDRAM Memory Models
      • SRAM Memory Models
      • Non volatile Memory Models
      • DIMM Memory Models
      • Misc Memory Models
      • DFI Verification IP's
    • SimXL - Emulation Models
      • MIPI Synthesizable Transactors
      • Networking and SOC Synthesizable Transactors
      • Automotive And Serial Bus Synthesizable Transactors
      • Storage And Video Synthesizable Transactors
      • DDR SDRAM Memory Synthesizable Transactors
      • Low Power Memory Synthesizable Transactors
      • Graphics Memory Synthesizable Transactors
      • Flash Memory Synthesizable Transactors
      • High Bandwidth Memory Synthesizable Transactors
      • SDRAM Memory Synthesizable Transactors
      • SRAM Memory Synthesizable Transactors
      • DIMM Memory Synthesizable Transactors
      • Misc Memory Synthesizable Transactors
      • DFI Synthesizable Transactors
    • Formal Verification IP (Assertion IP)
      • Networking and SOC Assertion IP's
      • DDR SDRAM Memory Assertion IP's
      • Low Power Memory Assertion IP's
      • Graphics Memory Assertion IP's
      • SDRAM Memory Assertion IP's
      • DFI Assertion IP's
      • Serial Assertion IP's
    • Post Silicon Validation IP's
      • MIPI Post Silicon Validation IP's
    • Design IP's
      • MIPI Design IP's
      • Networking and SOC Design IP's
      • DMA Controller Design IP's
      • Automotive Design IP's
      • Serial Bus Design IP's
      • Audio Video Design IP's
      • Memory Controller Design IP's
  • Customers
  • News & Events
  • Support
  • Contact Us
Products

AMBA AXI4-Stream Synthesizable VIP

AMBA AXI4-Stream Synthesizable VIP

AMBA AXI4 Stream Synthesizable VIP provides a smart way to verify the ARM AMBA AXI4-Stream component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's AMBA AXI4-Stream Synthesizable VIP is fully compliant with standard AMBA AXI4 Stream Specification and provides the following features

Features
  • Compliant with the latest ARM AMBA AXI4-Stream Protocol Specification.
  • Supports AXI4-Stream Master and Slave.
  • Supports all AXI4-Stream data widths.
  • Support for all Data streams including Byte stream, Continuous aligned stream,Continuous unaligned stream and Sparse stream.
  • Support for single byte, packet and frame transfers.
  • Transfer interleaving support.
  • Support for upsizing, downsizing and merging.
  • Supports constrained randomization of protocol attributes.
  • Slave supports fine grain control of response.
  • Programmable wait states or delay insertion.
  • Ability to inject errors during transfer.
  • Ability to configure the width of all signals.
  • Support for bus inactivity detection and timeout.
  • Programmable Timeout insertion.
  • Rich set of configuration parameters to control AXI4-Stream functionality.
  • On-the-fly protocol and data checking.
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Callbacks in Master and Slave for various events.
  • Status counters for various events on bus
Benefits
  • Compatible with testbench writing using SmartDV VIP's
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms
AMBA AXI4-Stream Synthesizable VIP Env

    Note: Only mails from offical mail ID will be processed

    Request Datasheet
    Request Evaluation

    SmartDV's AMBA AXI4-Stream Synthesizable VIP Synthesizable env contains following:

  • Synthesizable transactors
  • Complete regression suite containing all the AMBA AXI4-Stream Synthesizable VIP testcases
  • Examples showing how to connect various components, and usage of Synthesizable VIP
  • Detailed documentation of all class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

Give us your feedback

Was this page helpful?
Ask us a question or get help

Talk to Us

Partner with us

Develop Custom VIP's
Partner for design IP's

Send Enquiry

Quick Contact

A value is required.
A value is required.
A value is required.
A value is required.
Copyright © 2020 SmartDV Technologies India Private Limited All rights reserved.