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AMBA3/4 AXI/ACE/AXI4-Stream Synthesizable VIP

AMBA3/4 AXI/ACE/AXI4-Stream Synthesizable VIP

AMBA3/4 AXI/ACE/AXI4-Stream Synthesizable VIP provides a smart way to verify the ARM AMBA3/4 AXI/ACE/AXI4-Stream component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's AMBA3/4 AXI/ACE/AXI4-Stream Synthesizable VIP is fully compliant with standard AMBA 3/4 AXI, AXI4-Lite, AMBA4 ACE, AMBA4 ACE-Lite, AXI4-Stream Specification and provides the following features

Features
  • Compliant with the latest ARM AMBA 3/4 AXI, AXI4-Lite, AMBA4 ACE, AMBA4 ACE-Lite, AXI4-Stream specification
  • Supports AXI Master, AXI Slave, AXI Interconnect
  • Supports all ARM AMBA AXI 3.0/4.0 data and address widths
  • Supports all protocol transfer types, burst types, burst lengths and response types
  • Separate address/control, data and response phases. Separate read, write and snoop channels
  • Supports for burst-based transactions with only start address issued
  • Slave, Interconnect and Master support fine grain control of response per address or per transaction
  • Programmable wait states or delay insertion on different channels. Interconnect has the ability to replicate Master/Slave inserted delays
  • Ability to inject errors during data transfer
  • AXI3/AXI4/ACE/ACE-Lite Common support
    • Write strobe support to enable sparse data transfer on the write data bus
    • Narrow transfer support
    • Unaligned address access support
    • Ability to issue multiple outstanding transactions
    • Out of order transaction completion support
    • Write address independent response (Driving write data and providing response before address is accepted, after accepting all data)
    • Protected accesses with normal/privileged,secure/non-secure and data/instruction
    • Write data phase before Write address phase (negative AWVALID to WVALID delay)
    • Ability to configure the width of all signals
    • Conversion of different protocols and different data width
    • Configurable WID signal enable support for AXI4/ACE/ACE_LITE
  • AXI3 support
    • Write data and read data interleaving support
    • Configurable write and read interleave depth
    • Programmable interleave size per transaction to allow fixed and variable data interleaving in a transaction
    • Low-power Interface support
    • Atomic access support with normal access,exclusive access and locked access
  • AXI4 support
    • Read data interleaving support with programmable interleave depth and programmable interleave size per transaction to allow fixed and variable data interleaving in a transaction
    • Atomic access support with normal access and exclusive access
    • Longer bursts up to 256 beats
    • Quality of Service signaling
    • Multiple region interfaces
    • User signaling support
    • Ability to break longer bursts into multiple shorter bursts
    • Unmapped region address accesses
    • AWCACHE and ARCACHE Attributes
    • Low-power Interface support
  • AXI4-Lite support
    • Burst length of 1
    • Write strobe support
    • Data bus width of 32-bit or 64-bit
    • Ability to issue multiple outstanding transactions
  • ACE support
  • In addition to AXI4 features, ACE supports the following features:
    • Functionality to verify ACE and CCI interconnect functionality for cache
    • All ACE transaction types including Snoop, Evict, WriteEvict, Barrier and Distributed virtual memory (DVM) transactions
    • Multiple outstanding ACE transactions
    • All write/read responses and snoop responses
    • Cache model and snoop filtering
    • Fine grain control of Initiating Master transaction including main memory access
    • Fine grain control of Interconnect generated snoop transaction to snooped Masters
    • Fine grain control of Interconnect generated main memory access transactions
    • Fine grain control of Snooped Master’s response to a snoop transaction
  • ACE-Lite support
  • ACE-Lite has all the support similar to ACE, complying with the Specification for ACE-Lite specific features:
    • Barrier transactions
    • Shareable and Non-shareable transactions
    • Broadcast cache maintenance operations
  • AXI4-Stream support
    • Single byte, packet and frame transfers
    • All Data streams including Byte stream, Continuous aligned stream, Continuous unaligned stream and Sparse stream
    • Transfer interleaving support
    • Upsizing, downsizing and merging
  • Supports programmable timeout insertion
  • Supports FIFO memory
  • Supports rich set of configuration parameters to control AXI functionality
Benefits
  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms
AMBA3/4 AXI/ACE/AXI4-Stream Synthesizable VIP Env

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    SmartDV's AMBA3/4 AXI/ACE/AXI4-Stream Synthesizable env contains following:

  • Synthesizable transactors
  • Complete regression suite containing all the AMBA3/4 AXI/ACE/AXI4-Stream testcases
  • Examples showing how to connect various components, and usage of Synthesizable VIP
  • Detailed documentation of all class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

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